R. Nair, C. L. Berman, P. Hauge, and E. J. Yo#a. Generation of performance constraints for layout. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8(8):860--874, 1989. Home/Search Document Not in Database Summary Related Articles Check |
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Rectangle Replacement and Variable Ordering: Two Techniques for .. - Søe (1994) (Correct)
....the means of the transitive fanin dags, suggesting a depth first traversal of each input dag of node n in order to compute them before the node n. The order in which to traverse the input dags should be in decreasing order of height, thus computing the most compute intensive nodes first. Berman [Ber91] later related the order of traversal in Malik s heuristic to the problem of register allocation, saying that the height of a fanin dag can be taken as a rough estimate to the number of registers required to evaluate the function represented by the fanin dag. Again this is intuitively clear at ....
....heuristic. Instead of traversing the subdags in order of decreasing height, it traverses in order of decreasing count, where count is our technology independent area estimate. The use of count to sort the subdags is inspired by Berman s paper of relating ordering heuristics to register allocation [Ber91] Berman states that Malik s height heuristic is an approximation to the optimal register allocation technique as described in [SU70] By choosing the highest subdag first Malik et al. has achieved a rough estimate of the number of registers required to evaluate the logic. Intuitively we thought ....
C. Leonard Berman. Circuit width, register allocation, and reduced function graphs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-10(8):1059--1066, August 1991.
Integer Program Formulations of Global Routing and Placement .. - Lengauer, Lügering (1991) (1 citation) (Correct)
....feature in practical experiments with global routing. Furthermore, this observation enables us to incorporate additional side constraints into global routing. For instance, in timing driven layout, we often are only interested in wires whose length lies between specified lower and upper bounds [27]. In the explicit approach, we just render routings inadmissible that violate these constraints. As a general rule we can state: Whenever the number of routes is small or we are not concerned with Steiner tree computations, we can use the explicit approach. 2.2 The Implicit Approach The essential ....
R. Nair, C. L. Berman, P. S. Hauge, and E. J. Yoffa. Generation of performance constraints for layout. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-8(8):860--874, 1989.
Large-Scale Circuit Placement: Gap and Promise - Jason Cong Tim (Correct)
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R. Nair, C. L. Berman, P. Hauge, and E. J. Yo#a. Generation of performance constraints for layout. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8(8):860--874, 1989.
BEAR-FP: A Robust Framework for Floorplanning - Pedram, Kuh (1992) (Correct)
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R. Nair, C. L. Berman, P. S. Hauge, and E. J. Yoffa. Generation of performance constraints for layout. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-8(8):1989.
Large-Scale Circuit Placement: Gap and Promise - Jason Cong Tim (Correct)
No context found.
R. Nair, C. L. Berman, P. Hauge, and E. J. Yo#a. Generation of performance constraints for layout. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8(8):860--874, 1989.
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