G. Martin, "Design methodologies for system level IP," in Proc. Conf. Design Automation and Test Eur., Paris, France, Feb. 1998, pp. 286--289. Home/Search Document Details and Download
Summary Related Articles Check |
This paper is cited in the following contexts:
Hardware Reuse at the Behavioral Level - Schaumont, Cmar, Vernalde.. (1999) (7 citations) (Correct)
....this function is parameterized by the number of datapath registers per block, it cannot be obtained through simple instantiation. Therefore, introduction of this per block function requires significant RT coding overhead. This situation has been recognized by other authors as a Silicon Ceiling [7]. Research solutions have been either to encapsulate VHDL within an advanced design environment [6] or else to extend the semantics of VHDL itself [1, 2] Being faced with structural reuse problems in several recent demonstrator designs, we developed a hardware reuse mechanism at the more abstract ....
G. Martin. Design methodologies for system level ip. In Proc. DATE 1998, pages 286--302.
Polynomial Circuit Models for Component Matching in.. - Smith, De Micheli (2001) (Correct)
No context found.
G. Martin, "Design methodologies for system level IP," in Proc. Conf. Design Automation and Test Eur., Paris, France, Feb. 1998, pp. 286--289.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC