The Standard Performance Evaluation Corporation. WWW Site. http://www.spec.org, Dec. 2000.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....0.1 1 10 100 1000 25 0 25 50 75 100 125 Transistor Junction Temperature (C) Transistor Leakage (nanoamperes) Figure 1: Transistor leakage current (nA) for varying temperatures for the COM2 process. 2. 2 Benchmarks We evaluate our results using benchmarks from the SPEC CPU2000 suite [9]. The benchmarks are compiled and statically linked for the Alpha instruction set using the Compaq Alpha compiler with SPEC peak settings and include all linked libraries. For each program, we skip the first 1 billion instructions to avoid unrepresentative behavior at the beginning of the ....

The Standard Performance Evaluation Corporation. WWW Site. http://www.spec.org, Dec. 2000.

....Leakage currents are for 25 C. 0.01 0.1 1 10 100 1000 25 0 25 50 75 100 125 Transistor Junction Temperature (C) Figure 1: Transistor leakage current (nA) for varying temperatures for the COM2 process. 2. 2 Benchmarks We evaluate our results using benchmarks from the SPEC2000 suite [10]. The benchmarks are compiled and statically linked for the Alpha instruction set using the Compaq Alpha compiler with SPEC peak settings and include all linked libraries. For each program, we skip the first 1 billion instructions to avoid unrepresentative behavior at the beginning of the ....

The Standard Performance Evaluation Corporation. WWW Site. http://www.spec.org, Dec. 2000.

....we have incorporated a simulator modification that accurately models contention at the L1 L2 and memory buses [10] As in [10] the busses always give processor memory requests priority over hardware prefetch requests. 2. 2 Benchmarks We evaluate our results using the SPEC CPU2000 benchmark suite [21]. The benchmarks are compiled for the Alpha instruction set using the Compaq Alpha compiler with SPEC peak settings, which include aggressive software prefetching. Processor Core Clock rate 2GHZ Instruction Window 128 RUU, 128 LSQ Issue width 8 instructions per cycle Functional Units 8 ....

The Standard Performance Evaluation Corporation. WWW Site. http://www.spec.org, Dec. 2000.

....[5] The main processor and memory hierarchy parameters are shown in Table 1. For performance estimates and behavioral statistics, we use SimpleScalar s sim outorder simulator. For energy estimates, we use the Wattch simulator [2] Our results are evaluated using benchmarks from the SPEC2000 suite [18]. The benchmarks are compiled and statically linked for the Alpha ISA using the Compaq Alpha compiler with SPEC peak settings and include all linked libraries. We skip the first billion instructions of each program to avoid unrepresentative behavior at the beginning of the program s execution. We ....

The Standard Performance Evaluation Corporation. WWW Site. http://www.spec.org, Dec. 2000.

....respects the Intel PIII processor [4] The main processor and memory hierarchy parameters are shown in Table I. For state losing techniques, our simulations capture the extra delay and dynamic energy dissipation of induced misses. Results are evaluated using benchmarks from the SPEC CPU2000 suite [16]. Benchmarks are compiled and statically linked for the Alpha instruction set using the Compaq Alpha compiler with SPEC peak settings and include all linked libraries. For each program, we skip the first billion instructions to avoid unrepresentative behavior at the beginning of the program s ....

The Standard Performance Evaluation Corporation. WWW Site. http://www.spec.org, Dec. 2000.

....three additional stages between decode and issue. For Wattch, it is necessary to specify technology parameters and clock speed. We chose a feature size of #####, a # ## of 1.9V, and a clock speed of 1 GHz. 2. 2 Benchmarks We evaluate our results using benchmarks from the SPEC CPU2000 suite [17]. The benchmarks are compiled and statically linked for the Alpha instruction set using the Compaq Alpha compiler with SPEC peak settings and include all linked libraries. For each program, we skip the first 1 billion instructions to avoid unrepresentative behavior at the beginning of the ....

The Standard Performance Evaluation Corporation. WWW Site. http://www.spec.org, Dec. 2000.

....[14] Our model processor has sizing parameters that closely resemble Alpha 21264 [5] but without a clustered organization. The main processor and memory hierarchy parameters are shown in Table 1. 2. 2 Benchmarks We evaluate our results using benchmarks from the SPEC CPU2000 benchmark suite [18]. The benchmarks are compiled for the Alpha instruction set using the Compaq Alpha compiler with SPEC peak settings. For Processor Core Instruction Window 80 RUU, 40 LSQ Issue width 4 instructions per cycle Functional Units 4 IntALU,1 IntMult Div, 4 FPALU,1 FPMult Div, 2 MemPorts Memory ....

The Standard Performance Evaluation Corporation. WWW Site. http://www.spec.org, Dec. 2000.

....framework [5] Our model processor has sizing parameters that closely resemble Alpha 21264 [9] but without a clustered organization. The main processor and memory hierarchy parameters are shown in Table 1. 3. 2 Benchmarks We evaluate our results using benchmarks from the SPEC CPU2000 [29] and MediaBench suites [22] The MediaBench applications help us demonstrate the utility of cache decay for applications with significant streaming data. The benchmarks are compiled for the Alpha instruction set using the Compaq Alpha compiler with SPEC peak settings. For each program, we follow ....

The Standard Performance Evaluation Corporation. WWW Site. http://www.spec.org, Dec. 2000.

....and the Web based management system that launches on the browser, delivers through the network and controls them. This allows di erent learning resources to be managed by heterogeneous management systems. Other standards are referred to course packaging [18] question and test interoperability [20], student tracking, capability de nitions, and manyothers. 3. SUPPORTING WEB BASED HIGHLY INTERACTIVEANDCOLLABORATIVE EDUCATIONAL APPLICATIONS 3.1 Overview Our framework is organized as shown in the layered architecture outlined in gure 1. In the lowest layer SimulNet relies on ....

....statuses: pass, fail, complete, incomplete, browse and notattempted) Figure 6 illustrates the de nition of prerequisites for a course element. The de nition of questionnaires and tests is also possible using our authoring tool. That definition is made using the IMS Question Test Speci cation [20] that speci es the data format for tests interoperability. 92 4.2 Coping with Practical Training: the Learning by doing Paradigm Web based learning must cope with practical training. There are two main approaches to implement WWW Internet based training laboratory environment: distant access ....

IMS. The IMS Question & Test Specication, version 1.0. WWW site. http://www.imsproject.org/question.

....process. The IEEE LTSC Public and Private Information (PAPI) speci cation [16] describes implementationindependent learner records organized in six categories: personal, relations, security, preference, performance and portfolio. Another important speci cation is the IMS Enterprise Data Model [19] aimed at administration purposes. Standardized de nitions for course structures are necessary to move courses from one system to another. In a similar way, learning managementenvironments need to understand the course structure to schedule the next student activity. The AICC guidelines for ....

IMS. The IMS Enterprise Specication, version 1.01. WWW site. http://www.imsproject.org/enterprise.

....the division between the learning contents and the Web based management system that launches on the browser, delivers through the network and controls them. This allows di erent learning resources to be managed by heterogeneous management systems. Other standards are referred to course packaging [18], question and test interoperability [20] student tracking, capability de nitions, and manyothers. 3. SUPPORTING WEB BASED HIGHLY INTERACTIVEANDCOLLABORATIVE EDUCATIONAL APPLICATIONS 3.1 Overview Our framework is organized as shown in the layered architecture outlined in gure 1. In the ....

IMS. The IMS Content&Packaging Specication, version 0.92. WWW site. http://www.imsproject.org/content.

....oldest ready instructions. Finally, the cache hierarchy is a conventional two level, non blocking organization with separate first level instruction and data caches. For these simulations, HydraScalar models a pipelined bus with a fixed fetch spacing. 3. 2 Benchmarks The SPEC integer benchmarks [33] are summarized in Table 2. Simulations use the provided reference inputs. All benchmarks are compiled using gcc O3 funroll loops ( O3 includes inlining) Simulations include all non kernel behavior, such as library code. We omit the floating point suite because those programs have excellent ....

The Standard Performance Evaluation Corporation. WWW Site. http://www.specbench.org, Dec. 1996.

....reducing input sizes. We hope to address these problems by examining three issues in this paper. ffl We characterize benchmark performance in terms of cache size and instruction window size to help cull the design space that researchers need to explore. For example, several SPECint benchmarks [59] fit in 8 K instruction caches; while the small I cache footprint of SPEC benchmarks is a common complaint, we provide detailed data showing this. Copyright c fl 1999 IEEE. In IEEE Transactions on Computers, 48(11) 1260 81, Nov. 1999. Personal use of this material is permitted. However, ....

....A BTB miss therefore only experiences a 2 cycle penalty. Indirect jumps need to read the register file, which we assume cannot be done from decode. When the BTB mispredicts these targets, the error is only detected in the writeback stage. B. Benchmarks We examine the SPEC integer benchmarks [59], summarized in Tables II and III, and use the provided reference inputs. Like any other suite, SPEC has its shortcomings: for example, many of the programs fit in small I caches. Because commercial workloads differ in some ways from the SPECint programs [35] users should exercise care in ....

The Standard Performance Evaluation Corporation. WWW Site. http://www.specbench.org, Dec. 1996.

....the model just described, but can issue up to 8 integer instructions; as many as 4 of these may instead be floating point instructions. The instruction window contains 128 entries and the firstlevel caches are 128 KBytes. B. Benchmarks These evaluations use not only the SPECint95 benchmarks [29], but also four other primarily integer benchmarks. The four other integer benchmarks have been added to show that the results in this work are not specific to characteristics of SPECint programs. Table II summarizes the benchmarks characteristics. All are compiled using gcc O3 funroll loops ....

The Standard Performance Evaluation Corporation. WWW Site. http://www.specbench.org, Dec. 1996.

....obtained using a single, short simulation window of just 50 million instructions. They key to obtaining accurate results is to choose this simulation window carefully, and in particular to avoid unrepresentative behavior at the beginning of programs execution. 1 Introduction The SPECint programs [23] typically run for billions of instructions using reference inputs. Even smaller inputs typically run for hundreds of millions. But the fastest, detailed, cycle accurate microarchitecture simulators still take about an hour to simulate 100 million instructions on an UltraSPARC II or Pentium Pro. ....

....jumps need to read the register file, which is at best expensive to do from decode and is therefore not supported in these models. When the BTB mispredicts these targets, the error is only detected in the writeback stage. 3. 2 Benchmarks This research focuses on the SPEC95 integer benchmarks [23], summarized in Tables 2 and 3, and uses the provided SPEC95 reference inputs. Like any other suite, SPEC has its shortcomings: for example, many of the programs fit in small instruction caches. Because commercial workloads di#er in some ways from the SPECint programs [14] users should exercise ....

The Standard Performance Evaluation Corporation. WWW Site. http://www.specbench.org, Dec. 1996.

....branch mispredictions, and focuses on multipath execution, a di#erent form of which this thesis explores in Chapter 7. Chapter 2 Experimental Methodology This section describes the simulation infrastructure used to conduct the studies in this dissertation, and the SPEC95 benchmark programs [98] used to obtain measurements. The SPEC programs run for billions or even hundreds of billions of cycles. Because cycle accurate simulators take a long time to simulate such programs to completion days or weeks for some of the benchmarks I have developed a way to select a single, 50 million ....

....jumps need to read the register file, which is at best expensive to do from decode and is therefore not supported in these models. When the BTB mispredicts these targets, the error is only detected in the writeback stage. 2. 2 Benchmarks This research focuses on the SPEC95 integer benchmarks [98], summarized in Tables 2.3 and 2.4, and uses the provided SPEC95 reference inputs. Like any other suite, SPEC has its shortcomings: for example, many of the programs fit in small instruction caches. Because commercial workloads di#er in some ways from the SPECint programs [63] users should ....

[Article contains additional citation context not shown here]

The Standard Performance Evaluation Corporation. WWW Site. http://www.specbench.org, Dec. 1996.

No context found.

The Standard Performance Evaluation Corporation. WWW Site. http://www.spec.org, Dec. 2000.

....L2 I D each 1MB, 4 way LRU, 64B blocks,12 cycle latency L2 Memory bus 64 bit wide, 400MHZ Memory Latency 70 cycles Prefetcher Prefetch MSHRs 32 Prefetch Request Queue 128 entries Table 2.1: Configuration of simulated processor. We evaluate our results using the SPEC CPU2000 benchmark suite [73]. The benchmarks are compiled for the Alpha instruction set using the Compaq Alpha compiler with SPEC peak settings. For each program, we skip the first 1 billion instructions to avoid unrepresentative behavior at the beginning of the program s execution. We then simulate 2 billion instructions ....

....on the SimpleScalar framework [8] Our model processor has sizing parameters that closely resemble Alpha 21264 [22] but without a clustered organization. The main processor and memory hierarchy parameters are shown in Table 3.1. We evaluate our results using benchmarks from the SPEC CPU2000 [73] and MediaBench suites [46] The MediaBench applications help us demonstrate the utility of cache decay for applications with significant streaming data. The benchmarks are compiled for the Alpha instruction set using the Compaq Alpha compiler with SPEC peak settings. For each program, we follow ....

[Article contains additional citation context not shown here]

The Standard Performance Evaluation Corporation. WWW Site. http://www.spec.org, Dec. 2000.

....and memory hierarchy parameters are shown in Table 1. Because contention can have important influence on performance, we have incorporated a simulator modification that accurately models contention at the L1 L2 and memory buses [12] We evaluate our results using the SPEC CPU2000 benchmark suite [21]. The benchmarks are compiled for the Alpha instruction set using the Compaq Alpha compiler with SPEC peak settings. For each program, we skip the first 1 billion instructions to avoid unrepresentative behavior at the beginning of the program s execution. We then simulate 2 billion instructions ....

The Standard Performance Evaluation Corporation. WWW Site. http://www.spec.org, Dec. 2000.

....sizes and issue widths. The parameters for the experiment are explained in Section 3.3. 3.1 Simulation Environment The reference simulator for this study is the cycle level simulator sim outorder from the SimpleScalar tool set. The workload simulated consists of the SPECInt95 integer benchmarks [23]. The default reference inputs are used for all runs. For all benchmarks, the first 100 million instructions that commit are simulated. Note that the performance results are not supposed to be representative of the overall parallelism that one could extract from the programs [21, 20] because the ....

The Standard Performance Evaluation Corporation. WWW Site. http://www.spec.org.

....Nevertheless, all other things being equal, better prediction improves performance. We restrict our measurements to prediction type and accuracy in order to focus on different predictors ability to exploit predictability. 3. 2 Benchmarks Our evaluations use not only the SPECint95 benchmarks [27], but also 4 other primarily integer benchmarks and three SPECfp95 benchmarks. Gnuchess comes from the IBS benchmark suite [28] and is GNU s implementation chess. The benchmark sets the computer to play itself and deactivates the X interface. Wolf is the timberwolf circuit router and comes from ....

The Standard Performance Evaluation Corporation. WWW Site. http://www.specbench.org, Dec. 1996.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC