K.-T. Cheng and V. D. Agrawal. A partial scan method for sequential circuits with feedback. In IEEE Trans. on Computers, volume 39, pages 544548, Apr. 1990.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....may become unacceptable. For such situations, partial scan designs have been proposed. In partial scan designs only a selected subset of the flip flops in a sequential circuit are included in the scanpath. Several methods to choose the flip flops to be included in the scan path have been proposed [CHEN90], GUPT90] LEE90] One of these proposals gives a method to use the structural information in a sequential circuit to determine the flip flops to be placed in a scan path [CHEN90] We briefly discuss this method. A sequential circuit is represented by a directed graph (digraph) called S graph. ....

....included in the scanpath. Several methods to choose the flip flops to be included in the scan path have been proposed [CHEN90] GUPT90] LEE90] One of these proposals gives a method to use the structural information in a sequential circuit to determine the flip flops to be placed in a scan path [CHEN90]. We briefly discuss this method. A sequential circuit is represented by a directed graph (digraph) called S graph. Each flipflop in a sequential circuit is represented by a node in the S graph. A directed edge exists in the S graph from node i to node j if the state of the flip flop represented ....

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K.T. Cheng and V. D. Agrawal, "A Partial Scan Method for Sequential Circuits with Feedback," IEEE Transactions on Computers, Vol. 39, No. 4, pp. 544-548, April 1990.

....between hardware sharing and sequential Automatic Test Pattern Generation (ATPG) methods. The presence of loops in a sequential circuit is a major source of problems for sequential ATPG. Partial scan is an effective technique to break loops in the cimuit by scanning a subset of flip flops (FF s) [6], 23] Empirical evidence shows that breaking all nontrivial (with at least two FF s) sequential cycles is an effective heuristic for making a circuit highly testable [6] 23] In this paper, we minimize the number of scan registers required to break all nontrivial loops in the datapath, and use ....

....sequential ATPG. Partial scan is an effective technique to break loops in the cimuit by scanning a subset of flip flops (FF s) 6] 23] Empirical evidence shows that breaking all nontrivial (with at least two FF s) sequential cycles is an effective heuristic for making a circuit highly testable [6], 23] In this paper, we minimize the number of scan registers required to break all nontrivial loops in the datapath, and use this number as a measure of testability. It has been demonstrated that a design can be synthesized from a high level specification in such a way that a relatively small ....

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K. T. Cheng and V. D. Agrawal, "A partial scan method for sequential circuits with feedback," IEEE Trans. Cornput., vol. 39, no. 4, pp. 544-548, 1990.

....Motivation ASIC designs, and in particular DSP Aic components, form one of the fastest growing segments of the semiconductor market. For example, while in recent years the compound growth of overall semiconductor market was about 20 , the compound annual growth of the DSP ASIC market was almost 40 . At the same time, it has been realized that cost of testing is an increasingly important part of DSP ASIC chip costs [19] sometimes as high as 40 of the overall cost. As behavioral level synthesis tools mature, a large percentage of DSP ASIC designs is done using CAD environments. However, ....

....in recent years the compound growth of overall semiconductor market was about 20 , the compound annual growth of the DSP ASIC market was almost 40 . At the same time, it has been realized that cost of testing is an increasingly important part of DSP ASIC chip costs [19] sometimes as high as 40 of the overall cost. As behavioral level synthesis tools mature, a large percentage of DSP ASIC designs is done using CAD environments. However, until recently very few h gh level synthesis tools addressed testability. Our goal in this paper is to develope a method for VLSI ASIC realization ....

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K.T Cheng, V.D. Agrawal: "A Partial Scan Method for Sequential Circuits with Feedback", IEEE Trans. on Computers Vol. 39. No. 4, pp. 544-$48 1990.

....data paths, kkk level testable, nonscan, testability measure, test points. I. INTRODUCTION A MONG the several design for testability (DFT) techniques that have been proposed to ease the task of sequential test pattern generation, the partial scan technique has become increasingly popular [1] [3] Unlike full scan, where all the flip flops (FF s) in the circuit are made observable and controllable, the partial scan technique selects Manuscript received October 4, 1994; revised July 27, 1995. This paper was recommended by Associate Editor K. T. Cheng. S. Dey was with C C Research ....

....synthesis for testability techniques summarized above, all the existing RT level techniques are scan based and cannot generate testable data paths without the use of scan. C. Testability of Sequential Circuits The dependencies of the FF s of a sequential circuit are captured by an S graph [1], 2] It has been empirically determined that sequential test generation complexity may grow exponentially with the length of cycles in the S graph [1] 2] An effective partial scan approach selects scan FF s in the minimum feedback vertex set (MFVS) of the S graph so that all loops, except ....

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K. Cheng and V. Agrawal, "A partial scan method for sequential circuits with feedback," IEEE Trans. Comput., vol. 39, pp. 544--548, Apr. 1990.

....chain. The size of a test vector set can be smaller by performing dynamic or static compaction [1] 2] to merge compatible test vectors. Some shift operations can be eliminated if consecutive test vectors have patterns in common [3] The number of scan flip flops can be reduced with partial scan [4] or multiple scan chain [5] 6] We try to reduce test application time in scan based design from a different perspective. Conventional scan based test environment adopts a test per scan approach [7] in which a scan cycle is the number of clock cycles required to shift the vector into a serial ....

K. T. Cheng and V. D. Agrwal, "A partial scan method for sequential circuits with feedback," IEEE Trans. Comput., vol. 39, pp. 544-548, Apr. 1990.

....with nominal hardware overhead. I. INTRODUCTION Several existing scan based design for testability techniques use heuristics based on the topology of a circuit, like breaking all loops, except self loops, and reduction of sequential depth, as ways to make sequential ATPG of circuits easy [4, 5, 14]. However, it has been observed that for many circuits, even when all loops are broken using scan FFs, and the sequential depth is low, the circuit remains difficult for sequential ATPG. This paper introduces a new DFT technique to supplement topology based DFT techniques like loop breaking, and ....

....to the data path are independently controllable. An exception is Genesis [2] but that system focuses on hierarchical test generation, and not gate level sequential ATPG, which is the focus of this work. Even when the controller is made highly testable by using a gatelevel DFT technique like [4, 14], and the data path is made highly testable by using either a gate level or high level DFT technique, a high test efficiency may not be achieved by gate level sequential ATPG for the combined controller data path circuit. In this paper, we address the problem of making a circuit composed of a ....

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K.T. Cheng and V.D. Agrawal. A Partial Scan Method for Sequential Circuits with Feedback. IEEE Transactions on Computers, 39(4):544 -- 548, April 1990.

....designs. II. SCAN AND NON SCAN DFT OF RT LEVEL DATA PATHS : AN I LLUSTRATION Figure 1(a) shows the register transfer (RT) level data path for 4th order IIR cascade filter, synthesized from behavioraldescription using the HYPER high level synthesis system [15] The corresponding register S Graph [16, 17, 6] in Figure 1(b) shows the dependencies between the registers of the data path. The register S graph reveals the existence of several loops involving the registers. As can be expected, sequential ATPG is very difficult for the data path,as indicated in Table 2bytherowOrig. The testability of the ....

....of the data path. The register S graph reveals the existence of several loops involving the registers. As can be expected, sequential ATPG is very difficult for the data path,as indicated in Table 2bytherowOrig. The testability of the data path can be improved using partial scan techniques [16, 17, 18] to break all the loops of the circuit. Since the MFVS of the S graph in Figure 1(b) is 3, breaking all the loops needs scanning at least 3 registers, namely LA1, LA2, and LM1. For the 20 bit IIR filter data path shown in Figure 1(a) 60 scan FFs are needed by the partial scan tool OPUS [18] and ....

K.T. Cheng and V.D. Agrawal. A Partial Scan Method for Sequential Circuits with Feedback. IEEE Transactions on Computers, 39(4):544 -- 548, April 1990.

....2 Previous Work An immense amount of work has been done in the area of flip flop selection for partial scan. The previous work done for the selection of flip flops for partial scan is usually classified into three major categories: testability analysis based [3] 6] structuralanalysis based [8] [18] and test generator based [9, 16, 19, 20, 21, 22] Some of these [9, 16] also use a combination of these approaches. The stated objectives and the constraints in all of these methods vary widely, thus rendering a quantitative comparison extremely difficult. For example, some methods target ....

....has been done on the identification of a Minimal Feedback Vertex Set (MFVS) which is the minimal set of flip flops which, if scanned, will break all loops in the circuit. Typically self loops are ignored since test generation complexity varies exponentially as the depth of cycle. Cheng and Agrawal [8] did pioneering work in cycle cutting. Their approach also limits the length of consecutive self loops in the circuit. Chakradhar et al.: 11] gave the first exact algorithm for determining the MFVS. They do this by using a partitioned branch and bound approach. The problem of determining the MFVS ....

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K.-T. Cheng and V. D. Agrawal, "A partial scan method for sequential circuits with feedback," IEEE Trans. Computers, vol. 39, no. 4, pp. 544--548, April, 1990.

....to that of partial scan insertion which has been solved by many methods. The goal is to minimize hardware overhead while improving fault coverage as much as possible. Many papers in partial scan break sequential loops since size of loops impacts test application time exponentially [2] 3] [4], 5] 6] In [7] Stroele and Wunderlich present an algorithm to break all sequential loops for pseudo random test with minimal hardware overhead using a branch and bound algorithm to select flip flops. Data correlation and its effects on pseudo random testability has been investigated by ....

....the value of an output Z, independent of the value of other inputs. IV. PARTIAL BIST INSERTION WITH NORMALIZED CORRELATION Normalized correlation along a path can be used to predict the impact of reconvergent fanout on correlation. For the purpose of partial BIST insertion, use the S graph [4] to model the interconnections between flip flops. The vertices of the S graph represent flip flops and primary inputs and outputs, and an edge between nodes v i and v j represents the existence of a combinational path from v i to v j . Reconvergent fanout paths involving flip flops are ....

K. T. Cheng, and V. D. Agrawal, "A Partial Scan Method for Sequential Circuits with Feedback," IEEE Transactions on Computers, Vol. 39, No. 4, April 1990, pp. 544-548.

....by configuring a subset of flip flops as a BIST register, either BILBO [7] or CBILBO [10] Because scan and BIST flip flops incur area and performance overhead, the chief goal of partial scan BIST insertion is to select the minimum number of flip flops which will enable high fault coverage. In [3] Cheng and Agrawal postulated that the maximum test length of a sequential circuit is exponentially dependent on the length of the longest sequential loop. This observation has led many researchers to use the elimination of loops as a goal to direct partial scan BIST insertion [6] 8] 5] 2] ....

....fanout V. BIST FLIP FLOP SELECTION ALGORITHM We evaluate the significance of reconvergent fanout by developing a test flip flop selection algorithm which breaks reconvergent fanout and sequential loops. We compare the results of our algorithm to the results of the algorithm presented in [3] to demonstrate the benefit of considering reconvergent fanout as well as sequential loops during test flip flop selection. The outline of our test flip flop selection algorithm D Q 2 D Q 1 3 A B C X Y path 1 path 1 path 2 path 2 Time Frame n 1 Time Frame n a. D Q 2 3 A B C ....

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K.-T. Cheng and V. D. Agrawal. A Partial Scan Method for Sequential Circuits with Feedback. IEEE Transactions on Computers, 39(4), April 1990.

....approaches have been proposed to select the Scan Flip Flops: a Structural Analysis of the circuit is sometimes performed in order to identify critical structures from the point of view of testability. Feedback loops have been addressed as the main source of troubles for the ATPG activity [ChAg90], and their removal through Scan Flip Flop insertion has been proposed. In [LeRe90] ChAg90] CBAg94] and [KuWu90] several algorithms have been described, which are able to determine minimal subsets of Flip Flops in the circuit that, if made scannable, break all the loops. Other papers ....

....of the circuit is sometimes performed in order to identify critical structures from the point of view of testability. Feedback loops have been addressed as the main source of troubles for the ATPG activity [ChAg90] and their removal through Scan Flip Flop insertion has been proposed. In [LeRe90] [ChAg90], CBAg94] and [KuWu90] several algorithms have been described, which are able to determine minimal subsets of Flip Flops in the circuit that, if made scannable, break all the loops. Other papers [KiKi90] propose the use of Deterministic Testability Measures for Scan Flip Flop selection; ....

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K.T. Cheng, V.D. Agrawal, "A Partial Scan Method for Sequential Circuits with Feedback," IEEE Trans. on Comp., Vol. 39, No. 4, April 1990, pp. 544-548

....a subset of flip flops in the circuit for scan. Reduction in area, power consumption and shorter test vector set are the advantages over full scan. The previous work done for the selection of flip flops for partial scan is usually classified into 3 major categories: structural analysis based [4] [9] testability analysis based [2, 3] and test generator based [5, 9, 12, 13, 14, 15, 19] Some of these [5, 9] also use a combination of these approaches. Structural analysis based techniques represent the circuit as a graph and attempt to remove all possible feedback by scanning flip flops. ....

....to CAS G. Since exhaustive test generation is time consuming, we modified Strategate to stop when a user specified number of aborted states have been generated. Once the mapping of these states onto the Sgraph is done, we proceed to enumerate the cycles. Since cycle enumeration is NP complete [4], we stop the search for cycles once we have user specified number of cycles. This limit is circuit specific. B Ranking Cycles and Flip flop Selection Once the cycles have been ranked, we pick up the cycle (say, #) with the highest value of the CSG to break. We would like to pick up the flip flop ....

K.-T. Cheng and V. D. Agrawal, "A partial scan method for sequential circuits with feedback," IEEE Trans. Computers, vol. 39, pp. 544--548, 1990.

....[9] The final circuits of the presented tool are gate level loop free. To achieve that, the presented high level synthesis tool generates loop free RT level structures. The gate level self loops are not eliminated, since it has been demonstrated that they do not make test generation complex [10]. As will be shown later, there are only two cases in which RT level self loops form gate level loops when the registers are transformed into flip flops and the operational units into gates. In order to break all the gatelevel loops, those RT level self loops are also eliminated. 2. Loop ....

K. T. Cheng, V. D. Agrawal: "A Partial scan method for sequential circuits with feedback". Proc. IEEE Trans. Comp., pp. 544-548. April, 1990.

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K.-T. Cheng and V. D. Agrawal. A partial scan method for sequential circuits with feedback. In IEEE Trans. on Computers, volume 39, pages 544548, Apr. 1990.

.... design [6] However, concerns about the full scan overheads of area, delay and test application time have motivated designers and researchers to explore partial scan techniques [1] A partial scan technique, in which scan flip flops break feedback paths, was proposed by Cheng and Agrawal [4], and Kunzmann and Wunderlich [13] The resulting acyclic sequential circuit is guaranteed to be initializable and has a This work was supported in part by the National Science Foundation grant MIP9714034. y Summer intern at Agere Systems, Murray Hill, NJ 07974. well defined sequential depth ....

K.-T. Cheng and V. D. Agrawal, "A Partial Scan Method for Sequential Circuits with Feedback," IEEE Trans. Computers, vol. 39, no. 4, pp. 544--548, Apr. 1990.

....(ATPG) In partial scan, a subset of FFs is scanned. Thus, hardware overhead and testing time are reduced over full scan. However, one must use a sequential ATPG program whose complexity is significantly greater than that of combinational ATPG used in the full scan design. Cheng and Agrawal [3, 8] and Kunzmann and Wunderlich [17] have proposed partial scan methods that break cycles to make the sequential structure acyclic in the test mode. An acyclic circuit has a finite maximum sequential depth (d) defined as the largest number of FFs on any path between This work was supported in part ....

....faults mask each other, we generate multiple fault tests. Our test generation system correctly deals with such situations and obtains a 100 fault efficiency. We assume that the given sequential circuit is synchronous and acyclic. The technique is also applicable to other circuits via partial scan [8] or resynthesis [9] 2 Test Generation Approach Our test generation method has three steps, combinational ATPG model generation, combinational test generation and test transformation. 2.1 Combinational ATPG model generation Gupta et al. 15] have defined a balanced sequential structure. ....

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K.-T. Cheng and V. D. Agrawal, "A Partial Scan Method for Sequential Circuits with Feedback," IEEE Trans. Computers, vol. 39, no. 4, pp. 544--548, Apr. 1990.

.... of the full scan design [6] However, concerns about the full scan overheads of area, delay and test time have motivated designers and researchers to explore partial scan techniques [1] A partial scan technique, in which scan flip flops break feedback paths, was proposed by Cheng and Agrawal [4], and Kunzmann and Wunderlich [13] The resulting acyclic This work was supported in part by the National Science Foundation grant MIP9714034. y Summer Intern (1998 and 1999) at Bell Labs, Murray Hill, NJ 07974. sequential circuit is guaranteed to be initializable and has a well defined ....

K.-T. Cheng and V. D. Agrawal, "A Partial Scan Method for Sequential Circuits with Feedback," IEEE Trans. Computers, vol. 39, no. 4, pp. 544--548, Apr. 1990.

....such that every single fault of the sequential circuit is represented by a singlefault in the combinational circuit. As a result, a conventional combinational ATPG can be used. The above procedure is only applicable to acyclic sequential circuits. However, a cycle cutting method of partial scan [8] allows an acyclic test mode in any general sequential circuit. Table 3 shows the results of combinational test generation for partial scan ISCAS 89 circuits. These circuits are sequential since they have one or more flip flops remaining after cutting all cycles. The first column, Circuit name, ....

K.-T. Cheng and V. D. Agrawal, "A Partial Scan Method for Sequential Circuits with Feedback," IEEE Trans. Computers, vol. 39, no. 4, pp. 544--548, Apr. 1990.

....of these experiments. The experiments were performed for transition faults of size equal to one clock cycle. The table shows the fault coverage and the number of vectors for k = 1, k = 2 and k = 3 for some partially scanned ISCAS89 ADDENDUM93 benchmark circuits. We use the cycle breaking method [24] to obtain the partial scan circuits. For case k = 2, under the described test generation scheme, the number of vectors is comparable or larger than twice the number of vectors generated under the conventional at speed scheme (k = 1) Therefore, with respect to these vectors, the doublet method ....

K.-T. Cheng and V. D. Agrawal. A Partial Scan Method for Sequential Circuits with Feedback. Trans. on CAD, 39(4):544--548, April 1990.

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K.-T. Cheng and V. D. Agrawal, "A partial scan method for sequential circuits with feedback", IEEE Transactions on Computers, vol. 39, April 1990.

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K. T. Cheng, and V. D. Agrawal, "A Partial Scan Method for Sequential Circuits with Feedback," IEEE Transactions on Computers, Vol. 39, No. 4, April 1990, pp. 544-548.

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K.-T. Cheng and V. D. Agrawal, "A partial scan method for sequential circuits with feedback", IEEE Transactions on Computers, vol. 39, April 1990.

No context found.

K. T. Cheng and V. D. Agarwal, "A partial scan method for sequential circuits with feedback," IEEE Trans. Comput., vol. 39, no. 4, pp. 544--548, 1990.

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K.T. Cheng, V.D. Agrawal: "A Partial Scan Method for Sequential Circuits with Feedback", IEEE Trans. on Computers, Vol. 39., No. 4, pp. 544548, 1990.

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Kwang-Ting Cheng and Vishwani D. Agrawal, A Partial Scan Method for Sequential Circuits with Feedback, IEEE Trans. on Computers, Vol. 39, No. 4, pp. 544-548, April 1990

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