C. Healy, R. Arnold, F. Muller, D. Whalley, and M. Harmon. Bounding Pipeline and Instruction Cache Performance. IEEE Transactions on Computers, 48(1), 1999.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....time bounds for programs can be directly derived from time bounds on their parts through simple rules [20] Treebased calculation methods are straightforward, but cannot utilize complex flow constraints well. Path based techniques explicitly explore the execution paths of a program fragment [16, 24]. They can handle complex flow constraints somewhat better. The Implicit Path Enumeration Technique (IPET) finally, models possible program flows for (possibly unstructured) control flow graphs with arithmetic constraints [19, 22] Each entity i in the graph is given an execution time t i by the ....

C. Healy, R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, 48(1), Jan. 1999.

....measuring of execution times) by increasing the variability in execution time and by requiring more complex analysis methods. A variety of concrete analysis methods for pipelines have been proposed, ranging over cycle accurate simulators [6, 7, 22] special purpose models using reservation tables [4, 9, 14, 21], dependence graphs [15] abstract interpretation of pipeline behavior [8, 20] and tables of instruction execution times and inter instruction effects [2, 3] The timing benefit (effect) of pipelines is to a large extent due to the overlapping of pairs of adjacent instructions. This has ....

....Figure 8. There might be pipelines where such effects never actually materialize, but in most real life forking pipelines, this type of positive timing effects do occur and have to be accounted for in WCET analysis. Examples of such processors are the NEC V850E [18] MIPS R4000 [10] MicroSPARC I [9], and basically any processor employing a separate floating point pipeline. 4.4 LTEs Across Unbounded Number of Instructions It is not in general possible to provide a bound on the length of the sequences of instructions that can exhibit long timing effects. 10 # # # # # # # # # # # # # # # ....

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C. Healy, R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, 48(1), January 1999.

....many applications, the instruction cache achieves high hit rates for repetitive loops because the loop body is small enough to fit entirely into the cache. Only the first iteration will lead to cache misses while subsequent iterations will lead to hits. In the static cache analysis methodology in [3], a method to analyze the control flow of a program by statically categorizing the cache behavior of each instruction to always hit, always miss, first hit or first miss is introduced. The approach looks at the loop bodies starting at the innermost loop nest level. At each level, if the loops fits ....

C. Healy, R. Arnold, F. Muller, D. Whalley, and M. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, pages 53--70, January 1999.

....values, time and count, are intervals representing the worst case and best case bounds. As a result, the overall execution time is an interval, too. Many other approaches to task execution time analysis are also based on the analysis granularity of basic blocks or single basic block transitions [7] or require complex modifications to execution time determination [15] Very few approaches like [8] also consider more fine grain influences of complex processor architectures, e.g. pipelines and super scalar machines. The major drawback of such detailed approaches is state space explosion. The ....

C. Healy, R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, pages 53--70, January 1999.

....behavior and register allocation lead to a widely varying basic block execution time. This effect is referred to as overlapping basic block execution. Many other approaches to task execution time analysis are also based on the analysis granularity of basic blocks or single basic block transitions [8] or require complex modifications to execution time determination [15] Very few approaches like [9] also consider more fine grain influences of complex processor architectures, e.g. pipelines and super scalar machines. The major drawback of such detailed approaches is state space explosion. The ....

C. Healy, R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, pages 53--70, January 1999.

....A second issue is to set up correct and representative scenarios to be measured. If for instance the worst case execution time (WCET) is to be measured, one must set up an execution path that leads to the WCET. Execution time and other performance issues can either be statically analyzed [1, 2, 3, 4] or simulated[5, 6] or measured directly on the target system[4, 7] The advantage of static methods is that they are safe if the system model and analysis method are correct and compatible with each other. The hard part is to add complex structures into the model like pipelining, cache ....

C. Healy, R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, 48(1):53--70, January 1999.

....is either required or useful to tighten path description: how many times loops iterate, dependencies between if statements, etc. This information can be user provided (through annotations embedded in the source code [16] provided separately [10] or automatically obtained using flow analysis [7, 8, 6]. Early static WCET analysis give frameworks to analyze programs written in high level programming languages, but they often ignore the effect of modern architectural features, and thus lead to overestimated WCET. Some techniques have been defined to take into account the effects of architectural ....

....features, as for instance F. Mueller s static cache simula tion [14] which statically simulates all possible contents of the cache by considering possible execution paths all at once. Several works use static simulation techniques to take into account architectural features such as pipelines [5, 8, 21], instruction caches [14, 11, 8, 21] cache hierarchies [14] data caches [9] and branch prediction [3] Most timing analysis approaches that integrate several of the above static simulation techniques (usually cache and pipeline) into a single static WCET analysis method lead to static WCET ....

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C. Healy, R. Arnold, F. M511er, D. Whalley, and M. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, 48(1), January 1999.

....or provided separately [14, 17, 19, 30] However, to some extent the flow analysis can be automated [4, 13, 15 17, 23, 33] The low level analysis can be further divided into two stages. Global low level analysis takes features requiring a global view (caches, branch predictors) into account [5, 14, 16, 18, 20, 21, 24, 25, 33, 36]. Local low level analysis considers features with local effects, like pipelines and superscalar instruction execution [9, 10, 16, 21, 22, 32, 33] Three classes of calculation methods are mainly used: tree based calculation, pathbased calculation, and the Implicit Path Enumeration Technique ....

....further divided into two stages. Global low level analysis takes features requiring a global view (caches, branch predictors) into account [5, 14, 16, 18, 20, 21, 24, 25, 33, 36] Local low level analysis considers features with local effects, like pipelines and superscalar instruction execution [9, 10, 16, 21, 22, 32, 33]. Three classes of calculation methods are mainly used: tree based calculation, pathbased calculation, and the Implicit Path Enumeration Technique (IPET) The tree based approach is limited to well structured codes, and assumes that the execution time bounds for programs can be directly derived ....

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C. Healy, R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, 48(1), Jan. 1999.

....is either required or useful to tighten path description: how many times loops iterate, dependencies between if statements, etc. This information can be user provided (through annotations embedded in the source code [15] provided separately [10] or automatically obtained using flow analysis [7, 8, 6]. Some techniques have been defined to take into ac count the effects of architectural features, as for instance F. Mueller s static cache simulation [13] which statically simulates all possible contents of the cache by considering possible execution paths all at once. Several works use static ....

....features, as for instance F. Mueller s static cache simulation [13] which statically simulates all possible contents of the cache by considering possible execution paths all at once. Several works use static simulation techniques to take into account architectural features such as pipelines [5, 8, 20], instruction caches [13, 11, 8, 20] cache hierarchies [13] data caches [9] and branch prediction [2] Most timing analysis approaches that integrate several of the above static simulation techniques (usually cache and pipeline) into a single static WCET analysis method lead to static WCET ....

[Article contains additional citation context not shown here]

C. Healy, R. Arnold, F. Mtiller, D. Whalley, and M. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, 48(1), Jan. 1999.

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C. A. Healy, R. D. Arnold, F. Mueller, D. Whalley, and M. G. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, 48(1):53--70, Jan. 1999.

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C. A. Healy, R. D. Arnold, F. Mueller, D. Whalley, and M. G. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, 48(1):53--70, Jan. 1999.

....designer to budget enough processing power to handle worst case computational requirements and safely meet deadlines under any circumstance. Sophisticated timing analyzers can calculate safe, tight WCET bounds for tasks executing on single issue inorder pipelines with instruction and data caches [2,11,12,14,15,16,17,18,26,34,42]. However, the level of sophistication needed to safely and accurately analyze more complex architectures is formidable. Currently, there is no way to precisely specify microarchitectures with a full complement of high performance techniques (complex dynamic branch predictors, caches, deep ....

....loop bodies only require a few traversals to bound the WCET for the entire loop. We capture the worst case behavior of architectural components along execution paths and compose these paths for loops, functions, and, ultimately, the entire application, to derive cycle counts that bound the WCET [1,2,11,23,24,25,26,27,38,39,40]. Figure 1 shows the organization of the timing analysis environment, which has been adapted to model the VISA and the Simplescalar instruction set (PISA) 6] The application is compiled to assembly code using the gcc PISA compiler. Control flow and instruction data memory references are ....

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C. A. Healy, R. D. Arnold, F. Mueller, D. Whalley, and M. G. Harmon. Bounding pipeline and instruction cache performance. IEEE Trans. on Computers, 48(1):53--70, Jan. 1999.

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C. Healy, R. Arnold, F. Muller, D. Whalley, and M. Harmon. Bounding Pipeline and Instruction Cache Performance. IEEE Transactions on Computers, 48(1), 1999.

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Healy, C.A., Arnold, R.D., Mueller, F., Whalley, D., Harmon, M.G.: Bounding pipeline and instruction cache performance. IEEE Transaction on Computers 48 (1999) 53--70

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C. Healy, R. Arnold, F. Muller, D. Whalley, and M. Harmon. Bounding Pipeline and Instruction Cache Performance. IEEE Transactions on Computers, 48(1), Jan 1999.

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C. A. Healy, R. D. Arnold, F. Mueller, D. B. Whalley, and M. G. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, 48(1), 1999.

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C. Healy, R. Arnold, F. Muller, D. Whalley, and M. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, 48(1), January 1999.

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C. A. Healy, R. D. Arnold, F. Mueller, D. Whalley, and M. G. Harmon. Bounding Pipeline and Instruction Cache Performance. In IEEE Transactions on Computers, number 48 in 1, January 1999.

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C. A. Healy, R. D. Arnold, F. Mueller, D. Whalley and M. G. Harmon. "Bounding Pipeline and Instruction Cache Performance," IEEE Transaction on Computers. Vol. 48, no 1, pp. 53-70, February 1999.

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C. A. Healy, R. D. Arnold, F. Mueller, D. Whalley, and M. G. Harmon. Bounding Pipeline and Instruction Cache Performance. In IEEE Transactions on Computers, number 48 in 1, January 1999. old ID: HEALY:99.

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C. Healy, R. D. Arnold, F. Muller, D. Whalley, and M. Harmon. Bounding pipeline and instruction cache performance. Transactions of computers, 48:63--70, Jan. 1999.

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Healy, C.A., Arnold, R.D., Mueller, F., Whalley, D., Harmon, M.G.: Bounding pipeline and instruction cache performance. IEEE Transaction on Computers 48 (1999) 53--70

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C. A. Healy, R. D. Arnold, F. Mueller, D. Whalley, and M. G. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, 48(1):53-70, January 1999.

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C. Healy et al. Bounding pipeline and instruction cache performance. IEEE Trans. on Computers, 48(1), 1999.

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C. Healy, R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, 48(1), January 1999.

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