S. Hauck, T. W. Fry, M. M. Hosler, J. P. Kao. The Chimaera Reconfigurable Functional Unit. IEEE Symposium on FPGAs for Custom Computing Machines, pp. 87-96, 1997.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....possess 100 programmability. Currently, reconfigurable fabric is not only considered to be confined into standalone chips, but also is part of hybrid systems such as System On Chip (SoC) solutions. While one trend is towards embedding reconfigurable cores into SoCs with processors, DSPs, etc. [15, 2, 1, 3] another direction of new architectures considers integration of optimized cores and hardwired blocks with reconfigurable fabric. The main goal here is to utilize the optimized blocks to improve the system performance. Such programmable devices are targeted for a class of applications, such as DSP ....

S. Hauck, T. W. Fry, M. M. Hosler, and J. P. Kao. The chimaera reconfigurable functional unit, April 1997. IEEE Symposium on FPGAs for Custom Computing Machines.

....SIMD Within A Register (SWAR) operations. Lastly, we introduce an algorithm to identify RFUOPs in a basic block. Section 5 demonstrates some experimental results. We summarize this paper in Section 6. 2. RELATED WORK Several architectures have been proposed to integrate a processor with an FPGA [6,7,8,9,13,14,15]. The usage of the FPGA can be divided into two categories: FPGA as a coprocessor or FPGA as a functional unit. In the coprocessor schemes such as Garp[9] Napa[6] DISC[14] and PipeRench[7] the host processor is coupled with an FPGA based reconfigurable coprocessor. The coprocessor usually has ....

....which is several cycles or more. Therefore, these architectures tend to map a large portion of the application, e.g. a loop, into the FPGA. One calculation in the FPGA usually corresponds to a task that takes several hundred cycles or more. In the functional unit schemes such as Chimaera[8], OneChip[15] and PRISC[13] the host processor is integrated with an FPGA based Reconfigurable Functional Unit (RFU) One RFU Operation (RFUOP) can take on a task that usually requires several instructions on the host processor. As the functional unit is interfaced only with the register file, ....

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S. Hauck, T. W. Fry, M. M. Hosler, J. P. Ka, The Chimaera Reconfigurable Functional Unit, IEEE Symposium on FPGAs for Custom Computing Machines, 1997

....more fine grained computations. As it is tedious to manually find and map such fine grained computations, it is desirable to have a compiler to automatically perform the extraction and mapping. This thesis discusses a C compiler for a processor with an RFU. The target architecture is the Chimaera[1], which is an implementation of the processor RFU approach. We show how the compiler automatically extracts the computations suitable for the FPGA from the applications. We also discuss the implementation of a simulator for Chimaera. Finally, we evaluate the performance of the code generated by ....

....would make them prohibitive to apply. 5.3.4. Distribution of the register input number The register input number of an RFUOP sometimes affects the performance. If an RFUOP has too many register inputs, it may use up the register resources and lead to some spill codes. For example, x=a[0] a[1] a[2] a[3] may be calculated by the following sequence: r1=a[0] r2=a[1] r1=r1 r2;r2=a[2] r1=r1 r2;r2=a[3] r1=r1 r2 . Only two registers are used in such a scheme. However, if we optimize this sequence with an RFUOP, the sequence becomes r1=a[0] r2=a[1] r3=a[2] r4=a[3] r1=RFUOP #1,r1,r2,r3,r4 . ....

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Scott Hauck, et al., The Chimaera Reconfigurable Functional Unit, IEEE Symposium on FPGAs for Custom Computing Machines, CA, USA,1997.

....arrays (FPGAs) have been considered as a new and effective means of performing computation. The wide range of high performance applications that have been developed with FPGAs indicate the great successes of this technology. Now many systems such as Garp [Hauser97] OneChip [Wittig96] and Chimera [Hauck97] combine reconfigurable hardware with a standard generalpurpose processors to make the FPGAs suitable not only for specialized applications, but also for general purpose applications. In such systems, portions of an application suited to hardware implementation are mapped to the FPGA, while other ....

....Targeted at the Single Context FPGA model, Hauck98] described an algorithm that can reduce the reconfiguration overhead by a factor of 2. As technology moves forward more advanced devices and systems, such as Xilinx Virtex families, Xilinx XC6200 families, Garp [Hauser97] and Chimaera [Hauck97], can be partially reconfigured at run time. For a system containing a Partial Run Time Reconfigurable device, a configuration can be loaded into part of the device while the rest of the system continues computing. Compared with the Single Context FPGA, the Partial Run Time Reconfigurable devices ....

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S. Hauck, T. Fry, M. Hosler, J. Kao. The Chimaera Reconfigurable Functional Unit. IEEE Symposium on FPGAs for Custom Computing Machines, 1997.

....architecture [2] combines memory blocks, Versatile Programmable Blocks (embedded ASIC blocks that perform complex instructions) into a LUT based fabric. Many other academic projects can be called a hybrid reconfigurable system, for example Dynamically Programmable Gate Array (DPGA) 3] Chimaera [4] and RaPiD [5] In addition, several industrial projects fall into the category of hybrid reconfigurable systems. One example is the Virtex II devices from the new Xilinx Platform FPGAs [6] which embed high speed multipliers into their traditional LUT based FPGAs. Also, the CS2112 Reconfigurable ....

S. Hauck, T. W. Fry, M. M. Hosler, J. P. Kao, The Chimaera Reconfigurable Functional Unit, IEEE Symposium on FPGAs for Custom Computing Machines, 1997.

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S. Hauck, T. W. Fry, M. M. Hosler, J. P. Kao. The Chimaera Reconfigurable Functional Unit. IEEE Symposium on FPGAs for Custom Computing Machines, pp. 87-96, 1997.

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S. Hauck, T. W. Fry, M. M. Hosler, J. P. Kao. The Chimaera Reconfigurable Functional Unit. IEEE Symposium on FPGAs for Custom Computing Machines, pp. 87-96, 1997.

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S. Hauck, T. W. Fry, M. M. Hosler, J. P. Kao. The Chimaera Reconfigurable Functional Unit. IEEE Symposium on FPGAs for Custom Computing Machines, pp. 87-96, 1997.

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