J. M. Rabaey, C. Chu, P. Hoang, and M. Potkonjak, "Fast prototyping of datapath-intensive architectures," IEEE Des. Test. Comput.,vol.8, no. 2, pp. 40--51, 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....requires less design effort, assuming a template is synthesized only once for all its instances. Figure 4: Logic diagram of the circuit of figure 3; the four templates shown here form a circuit cover Several techniques for extraction of functional regularity have been proposed in the literature [3, 4, 8, 9, 10, 11, 12]. Most of these techniques focus on covering a circuit by templates, assuming that a library of templates is provided by the user. Very few techniques address the problem of generating a good set of templates. Given a library of templates, Corazao et al. 8, 11 ] address the problem of mapping a ....

....in the literature [3, 4, 8, 9, 10, 11, 12] Most of these techniques focus on covering a circuit by templates, assuming that a library of templates is provided by the user. Very few techniques address the problem of generating a good set of templates. Given a library of templates, Corazao et al. [8, 11 ] address the problem of mapping a circuit described at a behavioral level using templates from the target library. Their approach addresses several key subproblems, such as mding complete as well as partial matches of a template and selecting a good set of templates to optimize the clock period. ....

J. M. Rabaey, et al,. "Fast prototyping of datapath-intensive architectures," IEEE Design and Test of Computers, June 1991, pp. 40-51.

....data flow( SDF) model [5] We restrict our attention to homogeneous SDF( fl1# where each atomic operational unit consumes and produces exactly one sample per each input and output in every execution cycle. The syntax of a targeted computation is defined as a control data flow graph (ap G) [8]. The CDFG represents the computation as a flow graph with nodes data edges and control edges. The semantics underlying the syntax of the CDFG format is that of the SDF model. Behavioral synthesis transforms a given behavioral specifications into a RTL description from the input behavioral ....

....also chosen to be added in the bottleneck region. The restriction is established by the lifetime of the produced variables by opm which needs to be short compared to average lifetime of variables. As a scheduling and register assignment algorithm we have used the standard HYPER synthesis script [8]. The objective functions of both optimization procedures were augmented to accommodate the ranking of operations,variables, or nodes,and limited scope determined by the bottleneck region and its # neighborhood. 6. EXPERIMENTAL RESULTS The selected benchmarks for evaluating the e#ectiveness of ....

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J. Rabaey C. Chu P. Hoang and M. Potkonjak. Fast prototyping of data path intensive architectures. Design & Test of Computers Vol.8(8,H# pp.40--51 1991.

....flow graph (CDFG) and the set of timing constraints, most commonly throughput requirements. Modern datapath designs, invariably group registers in register files in order to better enable sharing of control logic and to facilitate area efficient layouts. We assume the dedicated register file model [11, 10] shown in figure where each register is connected to a single input of an execution unit, while each unit can send data to an a.rbitrary number of registers. This model is also 285 exceptionally well suited for implementing fault tolerance for yield enhancement. The control is synthesized by ....

J. Rabaey et al., "Fast Prototyping of Data Path Intensive Architectures," IEEE Design & Test, Vol. 8, No. 1, pp. 40-51, 1991.

....node consumes two and produces one sample on every execution. The SDF model is well suited for specification of computations in numerous application domains such as DSP, communications, and multimedia. The syntax of a targeted computation is defined as a hierarchical control data flow graph (CDFG) [10]. A CDFG represents the computation as a flow graph, with nodes, data edges, and control edges. Operation Scheduling is thus the process of partitioning the set of operations in a CDFG into groups such that the operations in the same group are executed concurrently in the same control step while ....

....a differentiator, several transforms (Hilbert, Wavelet, Winogradfft11) a seventh order IIR filter, and three FIR filters (Dsfir51, Dskais55, fir00) We use 0.25 micron technology. To obtain the results, we use HYPER which is a resource utilization driven complex heuristic synthesis package [10]. For each case, we synthesized and compared the results with and without the FLOF S RM as the objective function in HYPER. The experimental results are in Table 1. The first column contains the design name, followed by the number of nodes, the number of different types of operations in the graph, ....

J. Rabaey, et. al. "Fast Prototyping Of Data Path Intensive Architectures." IEEE Design and Test of Computers, Vol.8, pp.40-51, 1991.

....high level and system level synthesis systems) 1 Estimation tools. Several high level synthesis systems contain tools which display a sharp lower bounds on best achievable implementation under design and timing constraints. For example, Hyper has a suit of relaxation based estimation tools [Rab91] and provides information about intangible properties (e.g. regularity, temporal and spatial locality) which often have dominant role in influencing the quality of the final implementation [Gue94] 2 Guidance Rules for transformation ordering. Information about enabling disabling ....

J. Rabaey, et al.: "Fast Prototyping of Data Path Intensive Architecture", IEEE Design and Test, pp. 40-51, 1991.

....IEEE 1240 where Cj and 7) are the execution time and period of task respectively and R i = k, l)11 k i,l = 1 . Lr rkj3. For area and time estimation for individual tasks, we again use two techniques: fast and elaborated. Both techniques use the Hyper set of estimation tools [Rab91, Cha95]. The fast technique predicts the number of instances of hardware primitives at RT level using min bound technique. The accurate technique uses the Hyper LP statistical model to estimate the area of implementation. 3. MULTIRESOLUTION REFINEMENT The synthesis problem for hard real time ....

....estimation tools are used to obtain this information and the measure is quantified in the same way as for functional units. 4. A similar number of registers. The required number of registers is estimated using the Hyper estimation tools which calculate the maximum cutset of the dataflow graph [Rab91 ], as measured by the ratio of the estimated number of registers in the initial designs. Note that the preference measures based on different observations may be contradictory. In our previous attempt [Pot95] we used a rank based function of a similar set of observation to guide the search. ....

J. Rabaey, et al."Fast Prototyping of Datapath-Intensive Architectures", IEEE Design and Test of Computers, Vol. 8, No. 2, pp. 40-51, 1991.

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J. Rabaey, C. Chu, P. Hoang, and M. Potkonjak, "Fast prototyping of data path intensive architectures," IEEE Design & Test of Computers, Vol. 8, No. 2, pp. 40-51, June 1991.

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J. M. Rabaey, C. Chu, P. Hoang, and M. Potkonjak, "Fast Prototyping of Datapath-Intensive Architectures," IEEE Design & Test of Computers, pp. 40-51, June 1991.

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J. Rabaey, C. Chu, P. Hoang, and M. Potkonjak, "Fast prototyping of datapath-intensive architectures," IEEE Design and Test of Computers, Mag. vol. 8, no. 2, pp. 40--51, June 1991.

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J. Rabaey, C. Chu, P. Hoang, and M. Potkonjak, "Fast prototyping of data path intensive architectures," IEEE Des. Test Comput., vol. 8, no. 2, pp. 40--51, Feb. 1991.

....datapath is shown in Fig. 4. As shown in row 4IIR.20 in Table 1, only one scan register is sufficient to break all loops in the datapath, and the datapath is highly testable. The hardware requirements are reduced to only two multipliers, one adder and one subtracter. Simulation using Hyper [35] indicates that all the computational structures of the fourth order parallel IIR filter, shown in Fig. 1 and Fig. 3(a) c) have identical numerical properties and therefore identical word length requirements. C. Paper Organization The rest of the paper is organized in the following way. In ....

....register file model of architecture. First, the model dictates grouping of single read, single write register files which enables area efficient layout. This is the main reason that the register file model is widely used in general purpose architectures [31] as well as custom ASIC designs [11] [35]. Next, it has been demonstrated that the dedicated register file model reduces the number of interconnect at the expense of a somewhat higher number of registers. As the technology scales, the reduction of interconnect is becoming more important, making the dedicated register file model even more ....

[Article contains additional citation context not shown here]

J. Rabaey, C. Chu, P. Hoang, and M. Potkonjak, "Fast prototyping of datapath-intensive architectures," IEEE Design and Test of Computers, vol. 8, no. 2, pp. 40-51, June 1991.

....been based on the synchronous data flow model of computation. As pointed out earlier, most high level synthesis systems for DSP, video, and other numerically intensive applications either assume that all input and delay node samples are available at the same time (all phases are zero) 33] 34] [40] or indirectly assign values to the phases by using schedulers that incorporate techniques such as overlapped scheduling and software pipelining to generate complex time shapes [12] 25] 38] However, only recently has some limited work been done on relaxing the assumption that all phases are ....

....the th input, relative to the arrival of , the th sample at the first input. We call , which may be negative, the phase associated with the th input. The interface to the external world may require that the input phases be constrained to specific values. However, many highlevel synthesis systems [40] simplify scheduling by assuming that the th sample at each input arrives at the same time, i.e. for all . It must be noted that the timing parameters , and , for , are sufficient to completely characterize the timing associated with the inputs and the outputs. In other words, the external ....

[Article contains additional citation context not shown here]

J. Rabaey, C. Chu, P. Hoang, and M. Potkonjak, "Fast prototyping of datapath-intensive architectures," IEEE Design Test Comput. Mag., vol. 8, pp. 40--51, June 1991.

....simulations) as a function of supply voltage. Figure lb ,shows a plot of experimentally derived normalized delay vs. Van. Once again, the delay dependence on supply voltage was verified to be relatively independent of various logic functions and logic styles [1] 1.00 0.90 0.811 0.711 o.611 0. 50 0.411 0.311 0.20 O. 1C o.oCl.oo i I I I 2.00 3.00 4.00 5.00 Vdd Figure 1: Plot of normalized energy vs.Vad (la) and delay vs. Vad (lb) It is clear that operating at the lowest possible voltage is most desirable, however, this comes at the cost of increased delays and thus reduced ....

....of experimentally derived normalized delay vs. Van. Once again, the delay dependence on supply voltage was verified to be relatively independent of various logic functions and logic styles [1] 1.00 0.90 0.811 0.711 o.611 0.50 0.411 0.311 0.20 O. 1C o.oCl.oo i I I I 2.00 3.00 4. 00 5.00 Vdd Figure 1: Plot of normalized energy vs.Vad (la) and delay vs. Vad (lb) It is clear that operating at the lowest possible voltage is most desirable, however, this comes at the cost of increased delays and thus reduced throughput. However, by modifying the architecture through a variety ....

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Rabaey, C. Chu, P. Hoang, M. Potkonjak, "Fast Prototyping of Data Path Inten- sive Architecture", IEEE Design and Test, pp.40-51, 1991.

....a certain number of register files (each register file contains one or more registers) and that each register file can send data to exactly one EXU. At the same time, each EXU can send data to an arbitrary number of register files. This model is used in several high level synthesis systems [38] [39], as well as many manual applicationspecific integrated circuits and general purpose data paths [40] Note that although the discussions in this paper assume the dedicated register file model, the nonscan DFT techniques presented here are applicable to any arbitrary hardware model. We use the ....

....the proposed nonscan DFT process using a design example. II. SCAN AND NONSCAN DFT OF RT LEVEL DATA PATHS:ANILLUSTRATION Fig. 1(a) shows the RT level data path for the fourth order IIR cascade filter, synthesized from behavioral description [37] using the HYPER high level synthesis system [39]. The basic RT level components of a typical data path are EXU s (like adders, multipliers, arithmetic and logical units, and transfer units) registers, multiplexors, and interconnects. The data path in Fig. 1(a) has two adders, three multipliers, 12 multiplexors, and 12 registers, as shown by ....

[Article contains additional citation context not shown here]

J. Rabaey, C. Chu, P. Hoang, and M. Potkonjak, "Fast prototyping of data path intensive architectures," IEEE Design Test Comput. Mag., pp. 40--51, 1991.

....is often very involved, time consuming, and cumbersome lRao90] Choosing the best fast DCT algorithm for a particular image or video application is a non trivial task. In such situations, behavioral synthesis tools provide an excellent option for rapid exploration of the algorithmic design space [Rab91, McF90]. After a long period of academic research, behavioral synthesis recently entered into a more mature phase where several research and commercial behavioral synthesis tools have become available, providing a reliable and fast path from functional specifi cation to custom ASIC implementation. In ....

....space exploration. We coded all DCT algorithms in the applicative, functional, DSP programming language SILAGE which HYPER translates into the CDFG format. After the initial functional simulation, HYPER synthesizes the targeted design under the user specified set of timing (throughput) constraints [Rab91]. The synthesis procedure includes several high 65 0 8186 7310 9 95 4.00 ) 1995 IEEE # of # additions algorithm # of additions multiplications subtractions (T) # of shifts (T) dtrect 56 64 218 198 DIF 20 12 62 47 DIT 35 14 72 49 wang 26 21 95 81 lee 20 18 54 46 QR 25 16 79 60 givens 20 ....

[Article contains additional citation context not shown here]

I. Rabaey, C. Chu, P. Hoang, M. Potkonjak: "Fast Prototyping of Datapath-Intensive Architectures", IEEE Design and Test of Computers, Vol. 8, No. 2, pp. 40-51, June 1991.

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J. M. Rabaey, C. Chu, P. Hoang, and M. Potkonjak, "Fast prototyping of datapath-intensive architectures," IEEE Des. Test. Comput.,vol.8, no. 2, pp. 40--51, 1991.

No context found.

J. Rabaey, C. Chu, P. Hoang and M. Potkonjak, "Fast Prototyping of data path intensive architectures", IEEE Design and Testvol. 8, pp. 40-51, 1991.

No context found.

. J. Rabaey, et. al. "Fast Prototyping of Datapath-Intensive Architecture". IEEE Design and Test of Computer, pp40-51, 1991

No context found.

J. Rabaey, C. Chu, P. Hoang, and M. Potkonjak. Fast prototyping of datapath intensive architectures. IEEE Design and Test of Computers, 8(2):40--51, 1991.

No context found.

J. Rabaey, C. Chu, P. Hoang, and M. Potkonjak, "Fast prototyping of data path intensive architectures," IEEE Design Test Comput., vol. 8, pp. 40--51, June 1991.

No context found.

J. Rabaey, C. Chu, P. Hoang, and M. Potkonjak. Fast Prototyping of Datapath-Intensive Architectures. IEEE Design and Test, 8(2):40--51, June 1991.

No context found.

J. Rabaey, C. Chu, P. Hoang, and M. Potkonjak. Fast Prototyping of Datapath-Intensive Architectures. IEEE Design and Test, 8(2):40--51, June 1991.

No context found.

J. Rabaey, C. Chu, P. Hoang, and M. Potkonjak, "Fast Prototyping of Datapath-Intensive Architectures," IEEE Design and Test of Computer, vol. 8, no. 2, pp. 40--51, June 1991.

No context found.

J. Rabaey, C. Chu, P. Hoang, and M. Potkonjak, "Fast prototyping of data path intensive architectures," IEEE Design Test Comput., vol. 8, pp. 40--51, June 1991.

No context found.

J. Rabaey, C. Chu, P. Hoang, and M. Potkonjak, "Fast prototyping of datapath-intensive architectures," IEEE Design and Test of Computers, vol. 8, no. 6, pp. 40--51, June 1991.

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