H. Li and M. Maresca, Polymorphic-torus network, IEEE Trans. on Computers, C-38, 9, 1345-1351, 1989.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....segments. We use the notation DMBC(p, b, io) to denote a DMBC with p processors, b buses, and io I O ports lines per processor. Architecturally, the DMBC is also closely related to the reconfigurable networks of Ben Asher et al. 1] and the various reconfigurable mesh architectures proposed in [6, 8, 9, 10, 12, 13, 14, 22]. A DMBC(n, 1, 1) for example, is identical to a one dimensional RMESH, PARBUS, and MRN (see [17] for example, for a definition of these variants of a reconfigurable mesh) A DMBC(n,m, 1) may be viewed as a generalization of a one dimensional RMESH to the case of multiple buses and a DMBC(n, n, ....

H. Li and M. Maresca, Polymorphic-torus network, IEEE Trans. on Computers, C-38, 9, 1345-1351, 1989.

....x A preliminary version of this paper appeared in Int l Parallel Processing Symp. 1995 [19] 2 as hypercubes [1] Examples of machines with such topologies include the MasPar MP 1 [3] Intel Paragon, MIT J Machine [6] Tera HORIZON [17] Cray T3D [4, 13] and Polymorphic Torus [9]. A torus is a mesh with wrap around links. Although meshes and tori are generally regarded as close families, there are still some distinctions: i) As opposed to meshes, all nodes of a torus are topologically symmetric, ii) a torus has a smaller (about half) diameter compared to that of an ....

H. Li and M. Maresca. Polymorphic-torus network. IEEE Trans. on Comput., 38(9):1345--1351, Sept. 1989.

....in the area of the design of high performance bus based designs. In particular, a number of architectures featuring buses with various dynamically reconfigurable characteristics (REBS) have been proposed in the literature. The REBS models, including the RMESH [17] the Bit Model RMESH [4] the PT [9], the RN [2] and the REBSIS [15] have produced fast and elegant solutions to a large variety of application problems. These models, collectively, possess two very attractive features: 1) reduced diameter due to the use of bus structures, and (2) multiple architectural schemes due to the use of ....

H. Li and M Maresca, Polymorphic-torus network, IEEE Trans. Compt., C-38, 1345-1351, Sep. 1989.

....connected computer model in which the shape of the buses can be altered to suit the need of the programs in execution. It shares some basic features with the CHiP computer [41] mesh connected computers augmented with broadcast buses [35] the bus automaton [39] the polymorphic torus network [19], and the coterie network in the latest version of the Content Addressable Array Parallel Processor (CAAPP) 50] A reconfigurable mesh has been built by NEC which has 512 PEs [18] Researchers at IBM have implemented a reconfigurable mesh called polymorphictorus [19] An optical implementation of ....

.... the polymorphic torus network [19] and the coterie network in the latest version of the Content Addressable Array Parallel Processor (CAAPP) 50] A reconfigurable mesh has been built by NEC which has 512 PEs [18] Researchers at IBM have implemented a reconfigurable mesh called polymorphictorus [19]. An optical implementation of the reconfigurable mesh is suggested by Ben Asher and Schuster [2] This implementation employs Electrically controlled Directional Coupler (EDC) as a switch and optical fibers as buses. On the theoretical side, many efficient parallel algorithms have been developed ....

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H. Li and M. Maresca, "Polymorphic-Torus Network," IEEE Trans. Computers, vol. 38, no. 9, pp. 1,345-1,351, Sept. 1989.

....smaller. General Communication Many SIMD arrays have additional interPE communication networks. These have included the CM 2 packet switched network, which supports broadcast, reduction, and scans [34] the MasPar circuit switched network [2] and various networks based on broadcast buses [8, 20, 25, 29, 39]. Nearly all of these networks have the property that the communication takes from a few to a few thousand PE instruction cycles during which time the PEs are idle. Feedback from Array to Controller Nearly all SIMD array systems have a mechanism to summarize array information through a global OR ....

Li, H., and Maresca, M. Polymorphic Torus Network. IEEE Trans. on Computers C-38, 9 (1989), 1345-1351.

....Reconfigurable mesh (RMESH) architectures offer the needed efficiency and flexibility in interprocessor communications by allowing the network topology to change dynamically as required by the algorithm. Since the advances in VLSI technology has started offering hope for manufacturing such chips [1, 2] in recent years, researchers have shown an increased interest in designing efficient algorithms for such architectures [3, 4, 5, 6, 7] The maze routing problem can be simply defined as finding a shortest path between two terminals following the nonblocked cells in a mesh (see Fig. 1) VLSI ....

Li, H. and Maresca, M. Polymorphic-torus network. IEEE Trans. Comput., 38:1345-- 1351, September 1989.

....in parallel machines, hampering any increase in computational power from translating into increased performance of the same order of magnitude. To overcome the inefficiency of long distance communications among processors, bus systems have been recently added to a number of parallel machines [1 6]. If such a bus system can be dynamically changed, under program control, to suit communication needs among processors, it is referred to as reconfigurable. Examples include the bus automaton [6] the reconfigurable mesh [3,4] and the polymorphic torus [1,2] The computational model used ....

....added to a number of parallel machines [1 6] If such a bus system can be dynamically changed, under program control, to suit communication needs among processors, it is referred to as reconfigurable. Examples include the bus automaton [6] the reconfigurable mesh [3,4] and the polymorphic torus [1,2]. The computational model used throughout this work is the reconfigurable mesh. 1 An m n reconfigurable mesh consists of m n identical processors positioned on a rectangular array (refer to Figure 1) The processor located at (i , j ) 0i m 1; 0j n 1) is referred to as P (i , j ) Every ....

H. Li and M. Maresca, "Polymorphic-torus network," IEEE Transactions on Computers, vol. C-38, no. 9, pp. 1345-1351, 1989.

....same coterie. The switches of the coterie network can also be set so that columns and rows are isolated. Once this is done, the row and column buses can be arbitrarily segmented still further. The coterie network can thus emulate the mesh with reconfigurable buses [12] and the polymorphic torus [10]. 3 Permutation on a Mesh Much work has been done on the problem of sorting and routing on a mesh. Two models of computation have been used: an MPP model [3] which assumes SIMD processing, and the more general MIMD model. In the former no queues are used; in the latter queue size becomes a ....

H. Li and M.Maresca (1987): "Polymorphic-Torus Network," Proc. International Conference on Parallel Processing.

.... routing algorithms, analogous to software versions of virtual cutthrough and wormhole routing [14, 8] which use those and only those resources available on a variety of processors such as the Massively Parallel Processor (MPP) 5] the ICL DAP [13] the Blitzen [6] the Polymorphic Torus [21], and the Content Addressable Array Parallel Processor (CAAPP) 37] The models under consideration are presented in section 2. We follow in sections 3 and 4 with a summary of previous work and the requirements and constraints of our investigation. In section 5 we present the algorithms: the basic ....

....In this paper we consider the class of architectures known as SIMD mesh connected arrays, or meshes for short. Many different machines of this type have actually been built, or are in the process of being built: among the more recent are the MPP [5] CLIP 4 [9] DAP [13] Polymorphic Torus [21], CAAPP [37] Blitzen [6] and the MasPar MP 1 [24] The Mesh With Reconfigurable Buses [26] is primarily a theoretical model, but as it has many features in common with machines being built, we include it in our list as well. These machines all have their particular unique features and ....

Li H., and Maresca, M. Polymorphic Torus Network. IEEE Trans. on Comp. C-38, 9 (Sep. 1989), 1345-1351.

....large number of problems in image processing, computational geometry and pattern recognition [12, 11] Unfortunately, meshes suffer from major limitations when data need to be transferred over long distances. A natural solution to this problem was to add row and column buses to the existing meshes [5, 8, 9, 10]. These meshes, known as meshes with multiple broadcasting (MMB for short) have already been implemented and are currently available [13] At any time only one processor can broadcast its data on a given bus. On the other hand, all processors connected to a bus can concurrently read the data ....

H. Li and M. Maresca, "Polymorphic-torus network," IEEE Transactions on Computers, vol. C-38, no. 9, (1989) 1345--1351.

....processing, computational geometry and pattern recognition were developed on this platform [9, 10] Unfortunately, meshes suffer from major limitations when data need to be transferred over long distances. A natural solution to this problem was to add row and column buses to the existing meshes [4, 6, 7, 8]. These meshes, known as meshes with multiple broadcasting (MMB for short) have already been implemented and are currently available [11] At any time only one processor can broadcast its data on a given bus. On the other hand, all processors connected to a bus can concurrently read the data ....

H. Li and M. Maresca, "Polymorphic-torus network," IEEE Transactions on Computers, C-38 (1989) 1345--1351.

....coterie. One way the switches of the coterie network can be set is so the columns or rows are isolated. Once this is done, the row or column buses can be arbitrarily segmented still further. The coterie network can thus emulate the mesh with reconfigurable buses [12] and the polymorphic torus [10]. Another obvious use for the coterie network is in finding and labeling connected components. Each PE tests its four neighbors and compares the value with its own: if the values are equal, the PE closes its coterie switch in that direction; if not equal, the switch is opened. Using a standard ....

H. Li and M.Maresca (1987): "Polymorphic-Torus Network," Proc. International Conference on Parallel Processing.

....CHiP and consist of thousands of switches and processors. Suggested implementations are both electronic [X86, MKS89] and optic [TCS89, BS90a] A VLSI chip called YUPPIE (Yorktown Ultra Parallel Polymorphic Image Engine) has been implemented on a reconfigurable torus, also called polymorphic torus [LM89a, LM89b]. Another existing VLSI design is the CAL Chip, currently consisting of a 16 Theta 16 reconfigurable mesh of switches [GK89] 1.2 The Power of Reconfiguration Reconfigurable Networks outperform PRAM s in the computation of several natural problems. For example, consider the computation of the ....

H. Li and M. Maresca, Polymorphic-torus network, IEEE Trans. Comput., Vol. 38, No. 9, pp. 1345--1351, September 1989.

....within each problem instance are non uniform. In this article we examine the particular problems of computing parallel prefix and reduction on sets of data mapped to non uniform, contiguous aggregates of processing elements (PEs) in a SIMD processor array with a reconfigurable mesh network [18, 31, 19, 21]. We are specifically interested in the efficient computation of these function within all aggregates simultaneously while only using a single thread of control. This model is important because it represents an architecture in which it is possible for pixels to be mapped directly to unique PEs, ....

H. Li and M. Maresca, "Polymorphic Torus Network," IEEE Transactions on Computers, Volume C-38, pp. 1345-1351, September, 1989.

.... for their better scalability to larger networks, as opposed to more complex networks such as hypercubes [BP95] Examples of machines with such topologies include the MasPar MP 1 [Mas] Intel Paragon, MIT J Machine [DDF 89] Tera HORIZON [TS88] Cray T3D [Cra93, Oed93] Polymorphic Torus [LM89] Fujitsu AP 1000, and iWarp [BCC 88] A torus is a mesh with wrap around links. Although meshes and torii are generally regarded as close families, there are still some distinctions: i) As opposed to a mesh, all nodes of a torus are topologically symmetric, ii) a torus has a smaller (about ....

H. Li and M. Maresca. "Polymorphic-Torus Network". IEEE Trans. on Computing, 38(9):1345--1351, Sept. 1989.

....Recently, however, implementations were suggested for the RN model, involving a variety of newly developed technologies, including optical communication and optical computing devices. Several dynamically reconfiguring machines involving thousands of switches were actually built [TCS89, GK89, LM89, MKS89, WLH 87] showing that the RN model is implementable in massively parallel architectures. Motivated by the existing implementations, there has been some work on the algorithmic and computational aspects of the RN model. Nakatani [Nak87] considered comparison based operations like ....

H. Li and M. Maresca. Polymorphic-torus network. IEEE Trans. on Computers, 38(9):1345--1351, 1989.

....3 Computer Science Department, Colorado State University, Ft. Collins, CO 80523 U.S.A. gupta cs.colostate.edu] x A preliminary version of this paper appeared in Int l Parallel Processing Symp. 1995 [22] Paragon, MIT J Machine [5] Tera HORIZON [20] Cray T3D [4, 16] Polymorphic Torus [11], Fujitsu AP 1000, and iWarp [3] A torus is a mesh with wrap around links. Although meshes and tori are generally regarded as close families, there are still some distinctions: i) As opposed to meshes, all nodes of a torus are topologically symmetric, ii) a torus has a smaller (about half) ....

H. Li and M. Maresca. "Polymorphic-Torus Network". IEEE Trans. on Computing, 38(9):1345--1351, Sept. 1989.

....another side, one column per unit time. Efficient algorithms are presented for intermediate level vision tasks including histograming, connectivity, convexity and proximity. 1 Introduction The reconfigurable mesh was originally proposed as a massively parallel computing model in the mid 1980s [6, 4, 8]. A review of the algorithmic literature [7] suggests that the major emphasis has been on i) fundamental problems, including sorting and arithmetic, ii) problems involving regularly structured data, such as matrices and images, in areas such as graph theory and image processing, and iii) ....

H. Li and M. Maresca. Polymorphic-torus network. IEEE Trans. on Computers, 38(9):1345--1351, September 1989.

....Thus the communication pattern between processors is flexible, and moreover, it can be adjusted during the execution of an algorithm. There are many reconfigurable parallel processing systems such as the bus automaton [28] 29] the reconfigurable mesh [20] the polymorphic torus network [13], the processor arrays with reconfigurable bus system (abbreviated to PARBS) 32] and the cross bridge reconfigurable array of processors (abbreviated to CRAPS) 12] which are all functionally equivalent. Fig. 3. Two dimensional 4 2 4 reconfigurable mesh. The reconfigurable mesh has begun to ....

H. Li and M. Maresca, "Polymorphic-torus network," IEEE Trans. Comput., vol. 38, pp. 1345--1351, Sept. 1989.

.... Systems (PARBS) 2] the Gated Connection Network (GCN) 3] and the The work described in this paper has been supported in part by research grants from MURST (Ministero della Universit e della Ricerca Scientifica e Tecnologica) and CNR (Consiglio Nazionale delle Ricerche) Polymorphic Torus [6]. The compression technique proposed in this paper is carried out by dividing a region of pixels having same value or similar value into clusters using a technique similar to run length coding. As these clusters are regular polygons, they can be coded by means of the coordinates of their upper ....

H. Li and M. Maresca, Polymorphic-Torus Network, IEEE Trans. on Computers Vol. 38, Num. 9, pp. 1345-1351, (Sept. 1989).

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H. Li and M. Maresca, "Polymorphic-torus network", IEEE Trans. on Computers, C-38, 9, 1345-1351, 1989.

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H. Li and M. Maresca, "Polymorphic-torus network," IEEE Trans. on Computers, C-38, 9, 1345-1351, 1989.

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H. Li and M. Maresca, "Polymorphic-torus network," IEEE Trans. on Computers, C-38, 9, 1345-1351, 1989.

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H. Li and M. Maresca, "Polymorphic-Torus Network," IEEE Trans. Computers, vol. 38, no. 9, pp. 1,345--1,351, Sept. 1989.

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H. Li and M. Maresca, "Polymorphic-torus network", IEEE Trans. on Computers, C-38, 9, 1345-1351, 1989.

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