S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In International Conference on Supercomputing, pages 317--324, 1997. 4.7  Home/Search   Document Details and Download   Summary   Related Articles   Check

....within a real time operating system. Static timing analysis is a subject of research for some time. Here, the most general approach was presented by LI et al. 4] But in the end, all previous surveys were either limited to more basic RISC processors [4] 6] or to single architectural properties [3][2] Moreover, most obtained results were validated by simulation and not by using a realworld environment. LIM et al. 5] first introduced a analysis technique for multiple issue processors for their analysis framework ETS. But, they restricted their experiments to this feature and did not ....

S. Ghosh, M. Martonosi, and S. Malik. Cache Miss Equations: An Analytical Representation of Cache Misses. In Proceedings of the 11th ACM International Conference on Supercomputing, July 1997.

....locality analysis technique parameter (N) REAL a(N,N) b(N,N) c(N,N) do i = 1, N do j = 1, N do k = 1, N a(i,j) a(i,j) b(i,k) c(k,j) enddo enddo enddo Figure 1. Matrix multiply algorithm used in this work to perform loop tiling. In particular, we use Cache Miss Equations (CMEs) [3] to represent the cache behavior. Cache Miss Equations are a very accurate analytical model of the cache memory. They describe the cache behavior by means of diophantine equations, which allows us to use mathematical techniques to compute the locality of each memory reference. Unfortunately a ....

....that represent all the potential cache misses for the references in a loop nest. They describe the precise relationship among the iteration space, array sizes, base addresses, and the cache parameters for a loop nest. This section presents an overview of the CMEs. For more details about CMEs see [3, 6]. In order to generate CMEs, the reuse vectors [7] of all the references in a loop nest must be generated. Reuse vectors provide information about the potential reuses in the entire iteration space. Figure 1 shows the matrix multiply kernel. For instance, r = 0; 0; 1) is a reuse vector for ....

[Article contains additional citation context not shown here]

Somnath Ghosh, Margaret Martonosi, and Sharad Malik. Cache miss equations: an analytical representation of cache misses. In ICS97, 1997.

....these caches, interference misses can dominate the cache behavior, particularly for array based codes. It should be stressed that since the cache interferences occur in a highly irregular manner, it is very difficult to capture them accurately [11] Ghosh et al. proposed cache miss equations in [4] as an analytical framework to compute potential cache misses and direct code optimizations for cache behavior. 3.2 Data Reuse and Data Locality Data reuse and data locality concepts are discussed in [12] in detail. Basically, there are two types of data reuses: temporal reuse and spatial reuse. ....

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proc. of ICS'97.

....imprecise. Analytical methods model the cache behavior in such a way that information about the causes of the misses can be obtained. Unfortunately, they can have huge computation times, lack of accuracy and only suit for perfectly nested loops without conditionals. Cache Miss Equations (CMEs) [3] is another method that accurately describes the cache behavior by means of a set of equations. These diophantine equations constitute an analytical model of the cache memory that allows us to use mathematical techniques to gather information about the cache behavior. Unfortunately, a direct ....

....point independently of all other memory references. They estimate the miss ratio by means of sampling techniques. 1.1 Goals and Philosophy We present an implementation of analytical method to analyze the performance of the memory hierarchy. It is based on the Cache Miss Equations (CMEs) [3]. Like them, we set up a collection of equations that describe the cache behavior. As we mentioned before, we apply some statistics based and polyhedra techniques to reduce the execution time needed to obtain the miss ratio [2, 6] Unfortunately, the current method is limited to special forms of ....

Somnath Ghosh, Margaret Martonosi, and Sharad Malik. Cache miss equations: an analytical representation of cache misses. In International Conference on Supercomputing (ICS'97), 1997.

....class and do not model associativity. Tsai and Agarwal model data reference patterns to predict cache misses on a cache coherent multiprocessor [20] Our treatment of coherence cache misses is specialized for random write reductions. Static analysis of cache misses is another well studied topic [3, 7]. In comparison, we include coherence misses and TLB misses, but again are considerably restricted in the set of programs we model. 6. CONCLUSIONS In this paper, we have identified a new application for parallel performance prediction. We have developed a detailed analytical model for ....

S. Ghosh, M. Martonosi, and S. Malik. Cache Miss Equations: An Analytical Representation of Cache Misses. ACM Transactions on Programming Languages and Systems, 21(4):703--746, 1999.

.... which analytical models have been employed has been in studying the cache performance of particular types of algorithm, especially in the analysis of blocked algorithms [9, 3, 5] Attempts have been made at creating general purpose models that are both accurate and expressive, with some success [12, 6, 7], but in all cases limited to describing direct mapped caches. In this work we present novel analytical techniques for predicting the cache performance of a large class of loop nestings, for the general case of set associative caches (i.e. with direct mapped as the case with associativity one) ....

Somnath Ghosh, Margaret Martonosi, and Sharad Malik. Cache miss equa- tions: An analytical representation of cache misses. In Proceedings of the 11th A CM International Conference on Supercomputing, Vienna, Austria, July 1997.

....M(a) a (a mod L S ) where L S is the cache line size) and #, # denotes the address of a memory access implied by a specific combination of array reference (e.g. R A ) and iteration vector. For a direct mapped cache, the index uniquely determines 5 Using the terminology of Ghosh et al. [10, 11], we refer to a static read or write in a program as a reference, whereas a particular execution of that read or write at runtime is a memory access. 6 A memory line refers to a cache line sized and aligned block in memory, while a cache line refers to the actual block in cache to which a memory ....

....which satisfy equation (6) above, and its value is then defined by # = j i, where the smaller vector of i and j is extended by zeros to the size of the larger. In cases when the values of # may have a dependence on an iteration vector, say i,we write this as #(i) For comparison, reuse vectors [15, 10, 11] indicate the direction(s) in the iteration space along which one or several array references will access the same array element, rather than an array element that is potentially conflicting in cache. 3.3. COMPUTING CONFLICT VECTORS The mapping of array indices to memory locations, as well as ....

[Article contains additional citation context not shown here]

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proc.

....array restructuring which ours does not. Our cost model is more detailed in estimating the cache misses and therefore the real cost of the array references before and after remapping. Some related work has produced more accurate and expensive models of data locality, for example Ghosh et al. [5, 6], but we do not require this level of accuracy. Static data remapping for C and Fortran programs has typically been implemented with copying [16, 7, 9] The overheads are different than in Impulse, and a full experimental comparison is beyond the scope of this paper. 4. Cost Models This section ....

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses2. In Proceedings of the Row Size Original Impulse Speedup Cost Model Loop Speedup Impulse+LP Speedup Cost Model BS TP Permutation BS TP 129 25235679

.... have also been found to be helpful [26] Data layout optimizations such as padding and transpose have been shown to be useful in eliminating conflict misses and improving spatial locality [36] Several cache miss estimation techniques have been proposed to help guide data locality optimizations [16, 45]. Tiling has been proven useful for linear algebra codes [23, 45, 11] and multiple loop nests across time step loops [43] In comparison we apply tiling to 3D stencil codes which cannot be tiled with existing methods. Researchers have examined irregular computations mostly in the context of ....

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proceedings of the

....There are still few works on the impact of data layout on cache misses. Panda, Nicolau et.al. 13] apply padding after having determined the tile size by the method of [3] Run time improvements are modest because the additional cost of more complex index operation is not considered. Ghosh et.al. [6] use cache miss equations to select padding and tile size. They do not provide comprehensive experimental data on run times and miss rates, which we require for comparison. Cierniak and Li [2] also apply control flow as well as data transformations. Their paradigm of reference distance is most ....

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proceedings of the 11th International Conference on Supercomputing (ICS-97), pages 317--324, New York, July7--11 1997. ACM Press.

....loops. During height reduction they not only optimize for low reuse vectors, but also for high, non negative dependency vectors. Finally they optimize the tiled loops with height reduction. This algorithm does not choose tile sizes or pad sizes with respect to con ict misses. Gosh et al. GMM97, GMM99] develop a system to estimate all cache misses in a loop nest for scienti c programs. Their system represents a loop nest by several Diophantine equations. These equations are called Cache Miss Equations (CMEs) Each solution of the CMEs is a cache miss of the loop nest. CMEs consider ....

....nest perform well for the other nests. To decide on a good choice of layouts for all nests we need to evaluate the layouts for each nest with costs. The costs of changing the layout between loops can be obtained by evaluating the loops necessary to change the layout. We will use the algorithm by [GMM97] see chapter 3.3.1) that allows to compute the number of misses for a loop nest to evaluate the cache performance of a layout. The actual costs of address computations can be estimated by counting and rating the expensive arithmetic operations. These costs form a graph that is directed by the ....

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proceedings of the

....Xavier Vera, Antonio Gonz alez, Josep Llosa Computer Architecture Department Universitat Polit ecnica de Catalunya Barcelona Tel. 34 93 401 69 88 Fax 34 93 401 70 55 fnbermudo, xvera, antonio, josepllg ac.upc.es Contact Author: Antonio Gonz alez Abstract Cache Miss Equations (CME) [GMM97] is a method that accurately describes the cache behavior by means of polyhedra. Even though the computation cost of generating CME is a linear function of the number of references, to solve them is a very time consuming task and thus trying to study a whole program may be unfeasible. In this ....

....such as prefetching, blocking, padding and data layout. However, such software techniques require a compile time analysis of the locality. For instance, prefetching is only useful when applied selectively to those references that frequently miss in cache. Cache Miss Equations [GMM97] are a very accurate analytical model of the cache memory. They describe the cache behavior by means of diophantine equations, which allows us to use mathematical techniques to compute the locality of each memory reference. For instance, by solving CME one could compute the different types of ....

[Article contains additional citation context not shown here]

Somnath Ghosh, Margaret Martonosi, and Sharad Malik. Cache miss equations: an analytical representation of cache misses. In ICS97, 1997.

....the cache behavior. Systematic approaches to estimate the amount of misses restrict the optimizable programs as certain constraints need to be met. Further these tend not to be exact, i.e. do not permit an optimal choice out of the proposals. Others as the Cache Miss Equations proposed in [GMM97] are very hard to implement and computational intensive. Therefore we chose to simulate the behavior of the loop nest in terms of cache accesses. To control the runtime of the simulation we plan to employ a randomized simulation. By simulating only parts of the iteration space of a loop nest we ....

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proceedings of the

....of useless data into data structures. Rivera and Tseng [RT98] classify padding more precisely and provide comprehensive experimental results. Panda et.al. PNDN97] propose to combine padding with a tiling scheme. Their run time improvements are very small due to operation overhead. Ghosh et al. GMM97] use cache miss equations to select padding and tile size however they do not provide much experimental data. The gaps filled with useless data that are characteristic for padding are no longer required. Kandemir et.al. KCR 98] target exclusively at spatial locality. Merging is a simple but ....

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proceedings of the 11th International Conference on Supercomputing (ICS-97), pages 317-- 324, New York, July7--11 1997. ACM Press.

....conflicting data structures cannot be done relying just on hardware counters for any of the current microprocessors. Moreover, these tools can only analyze the locality exploited by the memory hierarchy of the actual microprocessor. Tools based on a static locality analysis (e.g. 18][7]) This approach is very fast since it has a negligible slowdown. However, it may be inaccurate for some programs due to the lack of information at compile time. For instance, loop bounds, initial addresses of data structures, size of array dimensions, etc. may be unknown at compile time, which ....

S. Ghosh, M. Martonosi and S. Malik, "Cache Miss Equations: an Analytical Representation of Cache Misses", in Procs. of Int. Conf. on Supercomputing (ICS'97), pp. 317324, July 1997

....used to compute the CME using samples of the iteration space. Section 4 shows the results obtained for the SPECfp benchmarks and demonstrates the accuracy of the proposed approach. Section 5 summarizes the related work and section 6 draws the main conclusions of this work. 2 Overview of CME CME [7] are an analysis framework that describes the behavior of a cache memory. 1 Briefly, the general idea is to obtain for each memory reference a set of constraints and equations defined over the iteration space that represent the cache misses. These equations make use of the reuse vectors [25] ....

....space that represent the cache misses. These equations make use of the reuse vectors [25] Each equation describes the iteration points where the reuse is not realized. This section presents an overview of the CME. For more details, the interested reader is referred to the original publications [7] [8] 2.1 Generating CME For each reuse vector, two kind of equations are generated: ffl Compulsory equations Given a reference, they represent the first time a memory line is touched. We may distinguish between spatial and temporal reuse: Temporal The reuse is not realized when the studied ....

[Article contains additional citation context not shown here]

Somnath Ghosh, Margaret Martonosi, and Sharad Malik. Cache miss equations: an analytical representation of cache misses. In ICS97, 1997.

.... have also been found to be helpful [26] Data layout optimizations such as padding and transpose have been shown to be useful in eliminating conflict misses and improving spatial locality [36] Several cache miss estimation techniques have been proposed to help guide data locality optimizations [16, 45]. Tiling has been proven useful for linear algebra codes [23, 45, 11] and multiple loop nests across time step loops [43] In comparison we apply tiling to 3D stencil codes which cannot be tiled with existing methods. Researchers have examined irregular computations mostly in the context of ....

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proceedings of the 1997 ACM International Conference on Supercomputing, Vienna, Austria, July 1997.

....# A = 1 # B = c # D = 1 G = # H = j # # # # # # # # A = 1 # B = c E = f # D = 1 G = # H = j # # # # # Figure 2: An example unification in attribute value matrix notation. in speed between processor and memory continues to grow, caching is an important consideration (Ghosh et al. 1997). 1 A straightforward approach to separate the scratch fields from the nodes would be to use a hash table to associate scratch structures with the addresses of nodes. The overhead of a hash table, however, may be significant. In general, any binding mechanism is bound to require some extra work. ....

S. Ghosh, M. Martonosi, and S. Malik. 1997. Cache miss equations: An analytical representation of cache misses. In Proceedings of the 11th International Conference on Supercomputing (ICS-97), pages 317-- 324, New York, July 7--11. ACM Press.

....and engineers. Because of trends in computer architectures, lessons learned here are also likely to prove very useful for other application domains, including image processing and high performance databases. 6 Related Work There has been much work on improving locality in scientific applications [3, 24, 25, 26, 39, 40, 57, 67, 69, 70, 79, 87]. Here we will focus on the work which is most relevant to our proposed research. A number of researchers have investigated tiling as a means of exploiting reuse. Lam, Rothberg, Wolf show conflict misses can severely degrade the performance of tiling [51] Wolf and Lam analyze temporal and ....

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proceedings of the 1997 ACM International Conference on Supercomputing, Vienna, Austria, July 1997.

....all statements to obtain the data accessed at a single product space point. 2. Boundary effects are ignored, which is justifiable for large arrays and loop bounds. 3. Conflict misses are ignored. Various techniques have been developed to find tile sizes that avoid some forms of conflict misses [7, 10, 15], but we do not use them in our current implementation. 4 Experimental Results In this section, we present results from our implementation for four important codes. All experiments were run on an SGI Octane workstation based on a R12000 chip running at 300MHz with 32 KB first level data cache and ....

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proceedings of the 11th International Conference on Supercomputing (ICS-97), pages 317--324, New York, July 1997. ACM Press.

....technique for multiVLIWprocessors. The proposed scheduler includes some heuristics for minimizing inter cluster register communication, based on the information provided by the data dependence graph. Besides, it implements a powerful memory locality analysis based on Cache Miss Equations [9], which guides the scheduling of memory instructions with the objective of minimizing inter cluster memory communications. Modulo Scheduling for a Fully Distributed Clustered VLIW Architecture Jess Snchez and Antonio Gonzlez Dept. of Computer Architecture Universitat Politcnica de Catalunya ....

....Equations Cache Miss Equations (CME) is an analytical framework to model the cache behavior that is very accurate for codes that make use of scalar variables and affine 1 array references, which is very common in numeric applications. This framework was proposed by Gosh, Martonosi and Malik [9]. CME describes the precise relationship among the iteration space, array sizes, base addresses and cache parameters for a loop nest. A direct solution of the CME is an NP problem, which makes it infeasible for many practical cases. The problem can basically be stated as counting integer points ....

S. Ghosh, M. Martonosi and S. Malik, "Cache Miss Equations: an Analytical Representation of Cache Misses", in Procs. of Int. Conf. on Supercomputing (ICS'97), pp. 317324, July 1997

....pattern to x in the inner loop. Changes in access patterns make locality optimizations more difficult. Compounding the problem, regular codes benefit because compilers can analyze data access patterns, using estimates of cache performance to guide loop and data transformations to improve locality [32, 46, 13]. In comparison, there is relatively little information at compile time concerning the locality properties of irregular programs. Researchers have demonstrated that the performance of irregular programs can be improved by applying a combination of computation and data layout transformations on ....

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proceedings of the 1997 ACM International Conference on Supercomputing, Vienna, Austria, July 1997.

.... have also been found to be helpful [27] Data layout optimizations such as padding and transpose have been shown to be useful in eliminating conflict misses and improving spatial locality [36] Several cache miss estimation techniques have been proposed to help guide data locality optimizations [17, 44]. Tiling has been proven useful for linear algebra codes [24, 44, 12] and multiple loop nests across time step loops [42] In comparison we apply tiling to 3D stencil codes which cannot be tiled with existing methods. Researchers have examined irregular computations mostly in the context of ....

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proceedings of the 1997 ACM International Conference on Supercomputing, Vienna, Austria, July 1997.

.... techniques havebeen proposed to help guide data locality optimizations [9, 33] These techniques can also be enhanced to take into account limited cache associativity [8, 30] More recently, Ghosh et al. developed symbolic cache representation which are highly accurate in predicting cache misses [11, 12, 13]. Their cache miss equations can be used to predict the number of cache misses for a computation, and also be used to guide compiler transformations such as tiling [14] A number of researchers have investigated tiling as 11 a means of exploiting reuse. Tiling was first proposed by Irigoin and ....

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proceedings of the 1997 ACM International Conference on Supercomputing, Vienna, Austria, July 1997.

....to x in the inner loop. Changes in access patterns make locality optimizations more difficult. 1 Compounding the problem, regular codes benefit because compilers can analyze data access patterns, using estimates of cache performance to guide loop and data transformations to improve locality [33, 49, 13]. In comparison, there is relatively little information at compile time concerning the locality properties of irregular programs. Researchers have demonstrated that the performance of irregular programs can be improved by applying a combination of computation and data layout transformations on ....

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proceedings of the 1997 ACM International Conference on Supercomputing, Vienna, Austria, July 1997.

.... techniques have been proposed to help guide data locality optimizations [9, 33] These techniques can also be enhanced to take into account limited cache associativity [8, 30] More recently, Ghosh et al. developed symbolic cache representation which are highly accurate in predicting cache misses [11, 12, 13]. Their cache miss equations can be used to predict the number of cache misses for a computation, and also be used to guide compiler transformations such as tiling [14] A number of researchers have investigated tiling as 11 a means of exploiting reuse. Tiling was first proposed by Irigoin and ....

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proceedings of the 1997 ACM International Conference on Supercomputing, Vienna, Austria, July 1997.

....short computation times, make more flexible the parametric study of the cache. Although many models extract input parameters from address traces [3] 4] 5] and combine them with cache definition parameters, more general purpose models have been developed taking as input the code to analyze [6], 7] 8] Nevertheless these models only consider dense algebra codes, with regular access patterns. There are very few works related to the analytic modeling of sparse codes, and their scope is very limited compared to ours. For example, 9] is restricted to the partial modeling (only taking ....

S. Ghosh, M. Martonosi and S. Malik, Cache Miss Equations: An Analytical Representation of Cache Misses, in Proc. 11th ACM Int'l. Conf. on Supercomputing (ICS'97), Vienna, Austria, July 1997, 317--324.

.... ed as another important source of performance degradation [20] Their quanti cation has been achieved by counting the number of integer solutions to so called cache miss equations, i.e. linear Diophantine equations that specify the cache line to which an array reference in a loop will be mapped [5]. Due to the complexity and expense of such accurate investigations, simpler heuristics have been proposed [15, 16] The padding inference algorithm presented in Section 2 extends this work with respect to selfinterference in several aspects. It does not assume a direct mapped cache but explicitly ....

S. Ghosh, M. Martonosi, and S. Malik. Cache Miss Equations: An Analytical Representation of Cache Misses. In Proceedings of the ACM International Conference on Supercomputing (ICS'97), Vienna, Austria, 1997.

No context found.

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In International Conference on Supercomputing, pages 317--324, 1997.

....similarity between the structure of TCPs and branch predictors, such knowledge would help to improve the indexing and correlating effectiveness of TCP. 7 Related Work Software prefetching, and more generally, compile time analysis of memory access behavior, has been studied by many researchers [7, 13, 14, 15, 16]. Mowry et al. successfully predict what data references will likely miss in scientific codes that mainly employ matrices [15] Ghosh et al. describe methods for generating and solving equations that give a detailed representation of cache misses in loop oriented scientific code. Such a framework ....

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In International Conference on Supercomputing, pages 317--324, 1997.

No context found.

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In International Conference on Supercomputing, pages 317--324, 1997. 4.7

No context found.

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proceedings of the 11th International Conference on Supercomputing (ICS-97), pages 317--324, New York, July7-- 11 1997. ACM Press.

No context found.

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proceedings of the 11th International Conference on Supercomputing (ICS-97), pages 317--324, New York, July 1997. ACM Press.

No context found.

S. Ghosh, M. Martonosi, and S. Malik. 1997. Cache miss equations: An analytical representation of cache misses. In Proceedings of the 11th International Conference on Supercomputing (ICS-97), pages 317--324, New York, July 7--11. ACM Press.

No context found.

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proceedings of the 11th International Conference on Supercomputing (ICS-97), pages 317--324, New York, July7--11 1997. ACM Press.

No context found.

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses2. In Proceedings of the 129 25235679 2065.

No context found.

S. Ghosh, M. Martonosi, and S. Malik. Cache Miss Equations: An Analytical Representation of Cache Misses. ACM Transactions on Programming Languages and Systems, 21(4):703-746, 1999.

No context found.

GHOSH, S., MARTONOSI, M., AND MALIK, S. Cache Miss Equations: An Analytical Representation of Cache Misses. In Proceedings of the 11th International Conference on Supercomputing (1997), ACM Press, pp. 317--324.

No context found.

S. Ghosh, M. Martonosi, and S. Malik, "Cache miss equations: An analytical representation of cache misses," in Proceedings of the 1997.

No context found.

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In 1997.

No context found.

S. Ghosh, M. Martonosi and S. Malik, "Cache Miss Equations: An Analytical Representation of Cache Misses," Proc. ACM Int'l. Conf. on Supercomputing (ICS'97), pp. 317-324, July 1997.

No context found.

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In 1997.

No context found.

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In International Conference on Supercomputing, pages 317--324, 1997. 4.7

No context found.

S. Ghosh, M. Martonosi, and S. Malik. Cache Miss Equations: An Analytical Representation of Cache Misses. Proceedings of the 11th ACM International Conference on Supercomputing, July, 1997.

No context found.

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In International Conference on Supercomputing, pages 317--324, 1997.

No context found.

S. Ghosh, M. Martonosi, and S. Malik. Cache Miss Equations: An Analytical Representation of Cache Misses. In Proc. of the Int. Conference on Supercomputing, pages 317-324, Vienna, Austria, 1997.

No context found.

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proceedings of the 1997.

No context found.

Somnath Ghosh, Margaret Martonosi, and Sharad Malik. Cache miss equations: an analytical representation of cache misses. In ICS97, 1997.

No context found.

Somnath Ghosh, Margaret Martonosi, and Sharad Malik. Cache miss equations: an analytical representation of cache misses. In ICS97, 1997.

No context found.

S. Ghosh, M. Martonosi, and S. Malik. Cache miss equations: An analytical representation of cache misses. In Proceedings of the 1997.

First 50 documents  Next 50

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC