Roman Kuznar and Franc Brglez, PROP: A Recursive Paradigm for Area-Efficient and Performance Oriented Partitioning of Large FPGA Netlists, International Conference on Computer Aided Design, pp644-649, 1995.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....of FBB, to solve the problem of multi way partitioning with area and pin constraints. Experimental results show that FBB MW outperforms previous approaches for multi FPGA partitioning. In particular, although FBB MW does not employ logic replication and logic re synthesis, it still outperforms [5,6] which allow replication and re synthesis for optimization. I. Introduction Circuit partitioning is a critical optimization in many subfields of VLSI CAD: any top down hierarchical approach to system design must rely on some underlying partitioning techniques. The partitioning solutions greatly ....

....by the Texas Advanced Research Program under Grant No. 003658288. some uphill moves. In subsequent work, Ku znar and Brglez [5] allow CLBs to be replicated, i.e. they introduce functional replication to minimize the inter device interconnection and total cost of devices. Ku znar and Brglez [6] proposed a greedy heuristic which combines logic resynthesis with replication based partitioning. Chou et al. 7] have proposed an algorithm to partition a circuit into a single type of FPGAs, such that the number of FPGAs is minimized. They use local ratio cut clustering to reduce the circuit ....

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Roman Kuznar and Franc Brglez, PROP: A Recursive Paradigm for Area-Efficient and Performance Oriented Partitioning of Large FPGA Netlists, International Conference on Computer Aided Design, pp644-649, 1995.

.... many partitioning algorithms developed that have as a primary goal the reduction of 10 inter partition communication, and which can split a design into multiple pieces, including algorithms designed specifically to map into multiple FPGAs [Kuznar93, Woo93, Kuznar94, Weinmann94, Chan95, Huang95b, Kuznar95, Fang96] One such algorithm [Chou94] is also designed to efficiently handle the large circuits encountered during logic emulation. Instead of partitioning the entire circuit, it instead focuses only on a small portion of the circuit at a time. Although this speeds up the partitioning, it may ....

R. Kuznar, F. Brglez, "PROP: A Recursive Paradigm for Area-Efficient and Performance Oriented Partitioning of Large FPGA Netlists", International Conference on Computer-Aided Design, pp. 644-649, 1995.

....length for a variety of computational VLSI circuits in [16] An extensive analysis of wire crossing minimization algorithms is available in [17] Figure 7 and classes of C1355. Here, we report result of wire crossings, balanced bi partition mincut, and placed routed layout: using DOT [12] PROP [18], and OASIS [19] Again, we notice a dramatic reduction in wire crossing after 8750 9450 10250 0 5 10 15 20 25 30 C1355 Mutants (ClassB) Mninimized wire crossing (DOT) 45 49.5 55.5 61.5 67.5 72 0 5 10 15 20 25 30 C1355 Mutants (ClassB) Mincut for bipartition (PROP) 245 260 280 300 320 0 5 ....

R. Kuznar and F. Brglez. PROP: A Recursive Paradigm for AreaEfficient and Performance Oriented Partitioning of Large FPGA Netlists . In IEEE Intl. Conf. Computer-Aided Design, November 1995.

....their size is commonly too big to allow an implementation on a single FPGA device. System partitioning on FPGAs assumes the definition of a number of blocks in such a way that each block satisfies a set of constraints. The primary objective of FPGA partitioning is the number of FPGA devices [11]. The problem is difficult as the gate capacity of FPGA chips is large with respect to their pins number. Thus, because of a rapid pins saturation, it is difficult to obtain good device fillings. Permission to make digital hard copy of all or part of this work ....

R. Kuznar, F. Brglez, B. Zajc, "PROP: A Recursive Paradigm for AreaEfficient and Performance Oriented Partitioning of Large FPGA Netlists", Proc. Int. Conf. on Computed- Aided Design (1995): 644-649.

....pins (I O) using the FunctionBus takes such reduction even further. In particular, performance and I O can be traded off by varying the bus size, as demonstrated using several examples. 1 Introduction Partitioning a system among multiple FPGA s has attracted extensive investigation [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11]. These approaches share one common feature: they each partition a system s structural implementation (i.e. a netlist) In [12] we demonstrate substantial advantages of automatically partitioning a system s functional specification rather than its structural implementation. A functional ....

R. Kuznar and F. Brglez, "PROP: A recursive paradigm for area-efficient and performance oriented partitioning for large FPGA netlists," in Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 644--649, 1995.

....that have been used in this process include MIS [38] SIS [39] XACT [40] and several versions of bipartitioning programs: from a relatively simple implementation of a partitioner in [41] to an 95 TR CBL 03.1 REUBEN: A Tcl Based Reusable Environment . 2 advanced implementation based on [42]. The implementation as described in [42] has been useful to demonstrate most of the current capabilities supported by REUBEN. Benchmarks that were retrieved from a public domain server and used for benchmarking include [43] and [44] 2 Background and Motivation In the field of design automation, ....

....MIS [38] SIS [39] XACT [40] and several versions of bipartitioning programs: from a relatively simple implementation of a partitioner in [41] to an 95 TR CBL 03.1 REUBEN: A Tcl Based Reusable Environment . 2 advanced implementation based on [42] The implementation as described in [42] has been useful to demonstrate most of the current capabilities supported by REUBEN. Benchmarks that were retrieved from a public domain server and used for benchmarking include [43] and [44] 2 Background and Motivation In the field of design automation, publications often report the results of ....

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R. Kuznar and F. Brglez. PROP: A Recursive Paradigm for Area-Efficient and Performance Oriented Partitioning of Large FPGA Netlists . In IEEE International Conference on Computer-Aided Design, November 1995.

....Section 5 summarizes a large number of experiments. 2 Background and Motivation We use a simple experiment in Figure 1 to illustrate the issues involved in generating equivalence classes that can be used for performance evaluation of algorithms. The three algorithms are: hmetis [15] and prop [16] for balanced netlist bi partitioning, and dot for rank order directed graph placement [14] The three equivalence classes are the isomorphism class as introduced in [13] the class of clones [4] and the class of mutants [5] All these classes correspond to the benchmark circuit C432. Briefly, we ....

....method to minimize any crossing that can be avoided. Snapshot of experiments. As a first test, we complete the experiments introduced in Figure 1 earlier. Again, we apply the three algorithms to all 64 netlist instances of the new sibling class: a partitioner hmetis [15] a partitioner prop [16], and a placer dot [14] The resulting distributions for the new class c432 sib are shown in Figure 7. Clearly, the distributions are very similar to the distributions for the underlying isomorphism classes of the reference netlists. It has also been verified, through the degree sequence test, ....

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R. Kuznar and F. Brglez. PROP: A Recursive Paradigm for Area-Efficient and Performance Oriented Partitioning of Large FPGA Netlists . In IEEE International Conference on Computer-Aided Design, pages 644--649, November 1995.

....program nodes in the workflow, but never at the same point in time. To motivate and illustrate the main ideas in our approach, we will repeatedly use an example of a non trivial workflow that implements a rather complex partitioning and optimization algorithm, based on the description provided in [30]. The algorithm in the illustrative workflow is a recursive application of a bi partitioning tool that partitions a large netlist into a tentative partition and a remainder. The tentative partition is optimized by a logic optimizer tool, and evaluated for fit into the largest device from the ....

R. Kuznar and F. Brglez. PROP: A Recursive Paradigm for Area-Efficient and Performance Oriented Partitioning of Large FPGA Netlists . In IEEE International Conference on Computer-Aided Design, November 1995.

....the GUI is designed with color coded nodes and edges, all nodes in this figure are depicted with white background for improved readability. This is an example of a non trivial workflow that implements a rather complex partitioning and optimization algorithm, based on the description provided in [21], and we will use it repeatedly to motivate and illustrate the main ideas in our approach. The algorithm implemented by the workflow in Figure 2 is a recursive application of a bi partitioning tool that partitions a large netlist into a tentative partition and a remainder. The tentative partition ....

R. Kuznar and F. Brglez. PROP: A Recursive Paradigm for AreaEfficient and Performance Oriented Partitioning of Large FPGA Netlists. In IEEE Intl. Conf. on Computer-Aided Design, November 1995.

....the quality of the mutation classes by comparing the performance of various physical design algorithms on (1) the isomorphism class and (2) the mutation class. The tools we used in this experiments are: 1) DOT [8] to generate circuit schematics and analyze the number of wire crossings; 2) PROP [9] to report the mincut of a balanced bipartition; 3) OASIS [10] to layout the circuits using standard cell place and route methodology and report layout area and wire length; 4) VPR [11] to place and route in an TABLE I Statistical summary of the distributions. Algorithm for for oe for ....

....of the distributions. Algorithm for for oe for oe for t test ISO MUT diff. ISO MUT diff. score WC (DOT[8] 3172 3249 2.4 515 530 3.0 1.3 Area (OASIS[10] 1.84 1.88 2.2 0.47 0.50 6.8 6.6 WL (OASIS[10] 2.30 2.39 4.1 0.10 0.11 5.6 6.8 WL (VPR[11] 2665 2696 1.2 109 105 4.1 2. 3 mincut (PROP[9]) 13.6 15.3 12 4.2 4.4 5.7 3.1 FPGA architecture and report the routing wire length. Results are shown in Figure 4 which shows the frequency distribution of the cost function for the respective algorithm. Table I shows the relevant statistics of these distributions, e.g. the mean ( the ....

R. Kuznar and F. Brglez. PROP: A Recursive Paradigm for AreaEfficient and Performance Oriented Partitioning of Large FPGA Netlists . In IEEE International Conference on Computer-Aided Design, pages 644--649, November 1995.

....is 13 (12 feedthrough nodes on a single net) The maximum fanout of mutants varies from 7 to 13, and the maximum netspan remains at 13. We submitted the original and all 100 mutants to various tools: 1) a graph plotting package [12] to measure the wire crossings, 2) a generalized partitioner [13] to measure the size of mincut of balanced 4 way partitions, 3) a test generation program [7] to measure the fault coverage, 4) a redundancy removal [7] to measure the number of 2 input combinational nodes after the removal, 5) a technology mapper SIS map [7] to measure the area and delay of ....

R. Kuznar and F. Brglez. PROP: A Recursive Paradigm for Area-Efficient and Performance Oriented Partitioning of Large FPGA Netlists . In IEEE International Conference on ComputerAided Design, pages 644--649, November 1995.

....as netlists with the same number of I Os, the same number of nodes and the same number of pins distributed across the same number of levels. Upon submitting this set of mutants to (a) a schematic generator [17] which minimizes the wire crossings at each level, and (b) a bi section partitioner [18] which minimizes the mincut, we observe that both the wire crossings and the mincut are random variables, giving rise to approximately normal distributions such as shown in Figure 8. This is not a coincidence, as reported by results of additional experiments in this section. 1750 1800 1900 2000 ....

....Our experiences with technology mapping as well as the layout tool available to us reveal only negligible variations compared to variations induced by signatureinvariant mutants and reported in Figure 9, 10 later in this section. However, for two particular algorithms, dot in [17] and PROP in [18], the isomorphic equivalence circuit class itself can induces a distribution that is almost comparable to the one induced by the signature invariant and shown in in Figure 8. Specifically, we can observe up to 6 and 5 in variations in reported wire crossing and mincut (compared to 6.5 and 8 in ....

R. Kuznar and F. Brglez. PROP: A Recursive Paradigm for AreaEfficient and Performance Oriented Partitioning of Large FPGA Netlists . In IEEE International Conference on Computer-Aided Design, pages 644--649, November 1995.

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