PASSOS, N., SHA, E., AND CHAO, L.-F. 1995. Multi-dimensional interleaving for time-andmemory design optimization. In Proceedings of the IEEE International Conference on Computer Design (Austin TX, Oct.). IEEE Computer Society Press, Los Alamitos, CA, 440 -- 445. Home/Search Document Details and Download
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Memory Reuse Analysis in the Polyhedral Model - D. Wilde, S. Rajopadhye (1996) (22 citations) (Correct)
....reuse (all uses must be over before a value is overwritten) and even formulate an optimization problem to minimize the memory, but they do not give any compact conditions on the space of possible solutions. Related problems are also studied in the high level synthesis community (see for example [12] and references therein) The usage table can also be a tool for static analysis of loop programs to determine communication optimizations. Most current parallelizing compilers perform such optimizations by index analysis, often with intelligent pattern matching, but do not use the polyhedral ....
N. Passos, E. Sha, and L-F. Chao. Multi-dimensional interleaving for time-andmemory design optimization. In ICCD: International Conference on Computer Design, pages 440--445, Austin, Tx, October 1995. IEEE.
A Parameterized Index-Generator for the Multi-Dimensional.. - Passos, Sha Self-citation (Passos Sha) (Correct)
....of the ASIC design. A linear time algorithm, applicable to multi dimensional (MD) problems, able to achieve a fully parallel system design, i.e. simultaneous execution of all the operations in the loop body, while maintaining the original number of required memory queues has been developed [11]. This new mechanism, based on fine grain parallelism is called multi dimensional interleaving. It requires a new execution order of the loop, which directly affects the loop bounds and indices. In this study we present a technique on how to implement the correct indices generation for that ....
....increment on the memory size. In [9] a fully parallel solution is achieved by applying a new execution order to the iterations in a given block size. In the multi dimensional interleaving method, the loop body, also known as one iteration, is modeled as a multi dimensional data flow graph (MDFG) [11]. The method improves the parallelism by restructuring the iteration space and the loop body without changing the original schedule vector, and consequently, not requiring additional queues. An expansion of the iteration space is applied to improve the potential of parallelism, while a compression ....
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N. L. Passos, E. H.-M. Sha, and L.-F. Chao, " MultiDimensional Interleaving for Time-and-Memory Design Optimization," in the Proc. of the International Conference on Computer Design, Oct., 1995, pp. 440-445.
Data and Memory Optimization Techniques for Embedded.. - Panda, Catthoor, Dutt, .. (2001) (14 citations) (Correct)
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PASSOS, N., SHA, E., AND CHAO, L.-F. 1995. Multi-dimensional interleaving for time-andmemory design optimization. In Proceedings of the IEEE International Conference on Computer Design (Austin TX, Oct.). IEEE Computer Society Press, Los Alamitos, CA, 440 -- 445.
Verification of Loop Transformations for Complex Data.. - Applications Cupak.. (Correct)
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N.Passos, E.Sha, L-F.Chao, "Multi-dimensional interleaving for time-and-memory design optimization", Proc. IEEE Int. Conf. on Computer Design, Austin TX, pp.440-445, Oct. 1995.
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