T. D. Hodes, B. A. McCoy, and G. Robins. Dynamically-wiresized Elmorebased routing constructions. In Proc. IEEE Int. Symp. on Circuits and Systems, pages 463--466, 1994.  Home/Search   Document Details and Download   Summary   Related Articles   Check

.... also been extended recently to explore multiple interconnect topologies at each subtree and use higher order RLC delay models based on efficient incremental moment computation in partially constructed routing trees [14] Other methods, such as iterative routing tree construction with wire sizing [36, 37] and com18 bining P tree topology with buffer insertion and wire sizing [38] have also been proposed. These algorithms are summarized in [9] We would like to point out that it was shown in [39, 40] that with sufficient buffer insertion, the wire sizing solution can be considerably simplified so ....

T. D. Hodes, B. A. McCoy, and G. Robins, "Dynamically-wiresized Elmore-based routing constructions," in Proc. IEEE Int. Symp. on Circuits and Systems, pp. 463--466, 1994.

.... wiresizing problem to minimize the maximum delay along a net is formulated as a posynomial program in [14] where a continuous solution is obtained by a sensitivity based algorithm and then mapped into a discrete solution, 2 while simultaneous topology construction and wiresizing was studied in [13]. These papers assumed a single source for each net until very recently the optimal wiresizing problem for interconnects with multiple sources was formulated and solved optimally in [4] This optimal multi source wiresizing algorithm is applicable to the single source problem as well, and runs ....

T. D. Hodes, et. al. "Dynamically-Wiresized Elmore-Based Routing Constructions," ISCAS'94, pp. 463466 (Vol. I).

....the wiring delay and routability can not be estimated accurately in buffer insertion. In the case of Steiner tree construction followed by buffer insertion and wire sizing, a Steiner tree optimized for delay does not necessarily result in a minimum delay wire sized buffered Steiner tree. Recently, [7, 11, 14] explored the possibility of combining these steps. A simple greedy algorithm was used in [7] for tree construction with wire sizing. 14] and [11] used Atree [4] and P tree [12] respectively, for tree construction combined with the buffer insertion in [6] This paper presents an efficient ....

....Steiner tree construction followed by buffer insertion and wire sizing, a Steiner tree optimized for delay does not necessarily result in a minimum delay wire sized buffered Steiner tree. Recently, 7, 11, 14] explored the possibility of combining these steps. A simple greedy algorithm was used in [7] for tree construction with wire sizing. 14] and [11] used Atree [4] and P tree [12] respectively, for tree construction combined with the buffer insertion in [6] This paper presents an efficient simultaneous algorithm for Steiner tree construction, buffer insertion, and wire sizing. The ....

T. D. Hodes, B. A. McCoy, and G. Robins, "DynamicallyWiresized Elmore-Based Routing Constructions," Proc. IEEE Int. Symp. Circuits Syst., 1994, pp.463-466.

....for some technologies i.e. each sink connects to a point very near the driver or to the driver itself. The practical utility of such topologies is unclear since the routing area they consume is so high and the congestion near the driver may be intolerable. The later work of Hodes et al. [19] had some success in reducing this tendency of SERT by incorporating the notion of wire sizing to drive the construction. Other performance driven routing work includes the A Tree algorithm of Cong et al. 6] which attempts to find a min area routing tree which is also a shortest paths tree. ....

.... for finding such high quality permutations can guarantee a solution at least as good as that of a given structure (e.g. a Minimum Spanning Tree or the result of another Steiner Tree heuristic) Thus, this work is a departure from the constructive greedy heuristics proposed in the past (e.g. 3] [19]) Our approach bears some similarity to the Alphabetic Tree approach of [49] in that both approaches draw their solutions from the set of binary trees induced by a sink permutation. However, our approach differs 42 in a number of fundamental ways. First, placement of Steiner nodes in [49] is ....

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T. D. Hodes, B. A. McCoy, G. Robins, "Dynamically-Wiresized Elmore-Based Routing Constructions," Proc. IEEE Intl. Symp. Circuits and Systems, 1994.

....the wiresizing is performed during interconnect construction. Furthermore, simultaneous interconnect construction, buffer insertion and sizing, and wiresizing has been studied in order to achieve even better designs. 4.4. 1 Dynamic Wiresizing during Topology Construction Hodes, McCoy and Robins [HoMR94] propose a method to do wiresizing dynamically during tree construction. They combine the Elmore Routing Tree (ERT) algorithm [BoKR93] Section 3.3) and the GWSA algorithm [CoLe93] Section 4.2.1) as follows: starting with a degenerate tree initially consisting of only the source pin, grow the ....

T. D. Hodes, B. A. McCoy, and G. Robins, "Dynamically-Wiresized Elmore-Based Routing Constructions," Proc. Int'l Symp. on Circuits and Systems, 1994, pp. 463-466.

....interconnect when feature sizes enter the sub micron range and will become more dramatic in the future. To combat this trend, many methods have been proposed recently to improve interconnect delay. Two such techniques are the focus of this paper: performance driven routing (e.g. 1] 6] 18] 14] [11]) and wire sizing (e.g. 4] 17] 16] We propose techniques for simultaneous routing and wire sizing to produce low area, high performance routing constructions. Our approach is a departure from previous methods in that we are able to explicitly capture the notion of an area delay tradeoff. As ....

....for some technologies i.e. each sink connects to a point very near the driver or to the driver itself. The practical utility of such topologies is unclear since the routing area they consume is so high and the congestion near the driver may be intolerable. The later work of Hodes et al. [11] had some success in reducing this tendency of SERT by incorporating the notion of wire sizing to drive the construction. Other performance driven routing work includes the A Tree algorithm of Cong et al. 6] which attempts to find a min area routing tree which is also a shortest paths tree. ....

[Article contains additional citation context not shown here]

T. D. Hodes, B. A. McCoy, G. Robins, "Dynamically-Wiresized Elmore-Based Routing Constructions, " Proc. IEEE Intl. Symp. Circuits and Systems, 1994.

....known routing constructions. Section 4 discusses the static greedy wiresizing algorithm. In Section 5 we develop our new heuristic which combines the low delay routing and dynamic wiresizing methods. Section 6 presents experimental results, and we conclude in Section 7. This work is to appear in [17]. 2 Problem Formulation Our overall goal is as follows: given an arbitrary set of pins with a designated source, we wish to electrically connect all the pins so that the maximum source sink signal propagation delay is minimized. Ideally, a routing algorithm will compute and optimize signal ....

T. D. Hodes, B. A. McCoy, and G. Robins, Dynamically-Wiresized Elmore-Based Routing Constructions, in Proc. IEEE Intl. Symp. Circuits and Systems (to appear), London, England, May 1994. 14

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T. D. Hodes, B. A. McCoy, and G. Robins. Dynamically-wiresized Elmorebased routing constructions. In Proc. IEEE Int. Symp. on Circuits and Systems, pages 463--466, 1994.

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