Haigeng Wang, Nikil Dutt, Alexandru Nicolau, and Kai-Yeung Sunny Siu, "High-level synthesis of scalable architectures for IIR filteres using multichip modules," in Proceedings of the 30th ACM IEEE Design Automation Conference, 1993. Home/Search Document Details and Download
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Application-Specific Clustered VLIW Datapaths: Early.. - Lapinskii, Jacome, de .. (2002) (5 citations) (Correct)
....in particular, by structuring a VLIW datapath into a set of clusters. Each cluster in the datapath contains a set of functional units connected to a local register file (see Figure 1) The idea of restricting connectivity is not new, and in fact has been extensively used in ASIP synthesis [4] [5], 6] 7] and in high performance computer architectures [8] Recent industry and research projects specifically targeting clustered VLIW architectures include [9] 10] 11] 12] 13] 14] In such architectures explicit data transfer operations are typically required to move data from one ....
Haigeng Wang, Nikil Dutt, Alexandru Nicolau, and Kai-Yeung Sunny Siu, "High-level synthesis of scalable architectures for IIR filteres using multichip modules," in Proceedings of the 30th ACM IEEE Design Automation Conference, 1993.
High-Level Synthesis of Scalable Architectures for IIR Filters .. - Haigeng Wang (1992) (1 citation) Self-citation (Wang Dutt Nicolau) (Correct)
....in the RF) and produces 1 output (to the dedicated write port in the RF) The remaining 3 read ports and 3 write ports in each RF are connected to the bidirectional buses. All processors in the multichip module operate synchronously. Each processor is similar to a VLIW machine as explained in [28]. A summary of our architectural charateristics is shown in Table 4. Note that we chose these specific ranges of the parameters for simulating the example in the following sections with realistic constraints; a larger design space can be generated by applying our technique to general ranges of ....
H. Wang, N. Dutt and A. Nicolau, "High-level synthesis of scalable architectures for IIR filters using multichip modules", Proceedings of the ACM/IEEE 30th Design Automation Conference, Dallas, Texas, June 1993.
High-Level Synthesis of Scalable Architectures for IIR Filters .. - Haigeng Wang (1992) (1 citation) Self-citation (Wang Dutt Nicolau) (Correct)
....units having different time constraints, has not been studied. The regular schedules presented in this paper aim to solve this problem. In the field of parallel computing, parallel evaluationof linear recurrences has been studied for quite some time [1, 5, 17] for which the review is given in [18]. However, the underlyingmodel differs from high level synthesis, since parallel computing typically deals with a number of identical, multi function processors, while high level synthesis deals with a variety of functional units that differ in several attributes (e.g. functionality, cost, ....
....sweep algorithm. Table 4 shows the performance improvement obtained by our regular schedules over the other two algorithms. The sample period is the average time in number of cycles required to produce a sample output, the reciprocal of which is the filter s sample rate. The details are given in [18]. The column titled # FU s gives the number of adders and multipliers used. Recall that a single processor in our MCM architecture has an adder and a multiplier. The column titled our schedule displays the sample period yielded by our regular schedule for each number of processors. The column ....
H. Wang, N. Dutt, A. Nicolau and K. S. Siu "High-level synthesis of scalable architectures for IIR filters using multi-chip modules", UCI ICS TR 92-104, October 1992.
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