M. Miranda, F. Catthoor, M. Janssen, and H. D. Man. ADOPT: efficient hardware address generation in distributed memory architectures. In Proceedings of the International Symposium on System Synthesis, pages 20 -- 25, Nov. 1996.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....generator using address decoders (CntAG) Both types of address generator were synthesized with Synopsys Design Compiler for a 0#18 CMOS process. The counter based style was chosen as the benchmark because, for regular access patterns, it performs better than arithmetic based address generators [7]. Note that we cannot compare SRAG with SFM because SFM is only a FIFO memory. The address sequences used are the write and read sequences for the array new img in the block matching motion estimation algorithm shown in Figure 7. This code segment defines the read sequence for new img which ....

....considered. The reuse of address circuity between different address sequences in space and time can greatly reduce the area resources required. As most modern high performance memory systems are based on distributed memory architectures, the interconnect and routing costs should also be considered [7]. Although we expect this decoder decoupling approach to reduce power dissipation, in this work we have not carried out a rigorous study of it. Furthermore, SRAG architecture is somewhat limited in its application and is very much targeted towards block based image processing applications and ....

M. Miranda, F. Catthoor, M. Janssen, and H. D. Man. ADOPT: efficient hardware address generation in distributed memory architectures. In Proceedings of the International Symposium on System Synthesis, pages 20 -- 25, Nov. 1996.

....Memory organization exploration environment Matisse is a design flow intended for system exploration and synthesis of embedded systems characterized by dynamic data storage and intensive data transfer. The four main steps of the Matisse design flow are as follows (see also Figure 4. 1) WCD96] MCJ96] MCJ98] SWC97] SYM98] During dynamic memory management refinement the actual structures of dynamic data types and virtual memories is decided. The goal of task concurrency management is to meet the overall real time requirements imposed to the application being designed. Physical ....

M. Miranda, F. Catthoor, M. Janssen, H. De Man, "Adopt: Efficient hardware address generation in distributed memory architectures", Proc. of 9th ACM/IEEE Intnl. Symp. on System-Level Synthesis, La Jolla CA, USA, pp. 20-25, Nov. 1996.

....at the address sequence level which we have shown [10] to be crucial to reduce the overall cost is almost not considered there. On the other hand, architecture exploration support for target styles different from counter based architectures, only have been addressed extensively in our context [11]. We have shown that both target styles can be very efficiently complemented when providing efficient selection criteria for these alternatives at early phases of the design process [12] showing that the impact on the final implementation cost can be of several orders of magnitude. Compared to ....

....selected from a library. Use is made here by us of a subset of the Cathedral 3 methodology for lowly multiplexed custom data path synthesis [13] This architecture style has been first proposed in our environment as an alternative to the iAGU style for the synthesis of address generators [10] [11]. However, it is also being incorporated in more recent design flows proposed in academia [20] For cACUs, the complete set of iterator states must be supplied by a local controller. Also data dependent values can be fed into the inputs of the ASU, and hence both run time and manifest data ....

[Article contains additional citation context not shown here]

M.Miranda, F.Catthoor, M.Janssen, H.De Man, ADOPT: Efficient hardware address generation in distributed memory architectures, Proc. 9th ACM/IEEE Intln. Symp. on System Synthesis, pp. 20-25, 1996.

.... To handle this complex arithmetic special hardware units have been used in processors, which may be either programmable or custom hardware[1, 2] Custom hardware generation solutions have received a lot of attention and a considerable amount of work has targeted optimising their overhead [2, 3]. However, specialised hardware units and or custom hardware generation solutions add to the design complexity and cost. On the other hand, most programmable multimedia and DSP processors [4, 5] have specialised address calculation units that provide special addressing modes, like the autoinc ....

....compilers for low level code generation. From our experiments, we deduce that the opportunities present at the high level are to a great extent complementary and decoupled from the ones currently exploited at the instruction level. Previous experience with the custom ACU oriented ADOPT approach [3], has shown that when the exploration optimisation is done at a higher level (e.g. the index address expression level) much lower hardware implementation costs and synthesis time are obtained. However, our ADOPT approach up to now was solely targeted for custom hardware generation. This paper ....

[Article contains additional citation context not shown here]

M.Miranda, F.Catthoor, M.Janssen, H.De Man, ADOPT: Efficient hardware address generation in distributed memory architectures, Intl. Symp. on System Synthesis, 1996.

.... To handle this complex arithmetic special hardware units have been used in processors, which may be either programmable or custom hardware[1, 2] Custom hardware generation solutions have received a lot of attention and a considerable amount of work has targeted optimising their overhead [2, 3]. However, specialised hardware units and or custom hardware generation solutions add to the design complexity and cost. On the other hand, most programmable multimedia and DSP processors [4, 5] have specialised address calculation units that provide special addressing modes, like the ....

....compilers for low level code generation. From our experiments, we deduce that the opportunities present at the highlevel are to a great extent complementary and decoupled from the ones currently exploited at the instruction level. Previous experience with the custom ACU oriented ADOPT approach [3], has shown that when the exploration optimisation is done at a higher level (e.g. the index address expression level) much lower hardware implementation costs and synthesis time are obtained. However, our ADOPT approach up to now was solely targeted for custom hardware generation. This paper ....

[Article contains additional citation context not shown here]

M.Miranda, F.Catthoor, M.Janssen, H.De Man, ADOPT: Efficient hardware address generation in distributed memory architectures, Intl. Symp. on System Synthesis, 1996.

....within real time constraints requires an optimized mapping of address expressions in the algorithm onto address arithmetic optimized for both area and power within a given throughput. Highlevel address optimization is a very error prone and tedious task if done manually. Therefore, a methodology [11] has been developed to reduce the cost overhead for address generation for both custom and instruction set processors. This methodology includes address expression splitting clustering, induction variable analysis, target architecture selection, and global scope algebraic optimizations. The most ....

M. Miranda, F. Catthoor, M. Janssen, and H. De Man. Adopt: Efficient hardware address generation in distributed memory architectures. In IEEE/ACM Proc. of the Intnl. Symposium on System Level Synthesis, 1996.

....component of any architecture which deals with data transfer intensive algorithms. The efficient access to the memories within real time constraints requires an optimized mapping of the address expressions in the algorithm onto address arithmetic optimized for both area and power. A methodology [11] has been developed to reduce the cost overhead for address generation for both custom and instruction set processors. This methodology includes address expression splitting clustering, induction variable analysis, target architecture selection, and global scope algebraic optimizations. In ....

M. Miranda et al. ADOPT: Efficient hardware address generation in distributed memory architectures. Proc. of the Int'l Symposium on System Level Synthesis, 1996.

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