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K. S. Trivedi. On the paging performance of array algorithms. IEEE Transactions on Computers, 26(10):93 -- 947, 1977.

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Using Speculative Execution to Automatically Hide I/O Latency - Chang (2001)   (1 citation)  (Correct)

....at compile time in order to understand the accesses that the application will make when it is executed. The compiler then transforms the application such that it will provide this information whenever it is executed, e.g. by inserting prefetch calls into the application. Early work by Trivedi [63] proposed using static analysis to insert prefetch calls, but the proposed analysis applied only to looping array codes that could be tiled (loop tiling [70] also called loop blocking, is a compiler transformation that modifies the way a loop is structured in order to, for example, increase ....

Kishor S. Trivedi. On the paging performance of array algorithms. IEEE Transactions on Computers, 26(10):938--947, 1977.


Automatic Compiler-Inserted I/O Prefetching for.. - Mowry, Demke, Krieger (1996)   (43 citations)  (Correct)

....Using application specific knowledge to assist memory management policies was studied by Malkawi and Patel [18] however they only considered retain ing needed pages in memory and did not consider prefetching. The most relevant work to our study was con ducted nearly twenty years ago by Trivedi [32], who looked at the use application access patterns extracted by a compiler to implement prepaging . Although the interface to the OS is nearly identical, there are some significant differences. First, Trivedi s compiler analysis was restricted to programs in which blocking could be performed ....

K.S. Trivedi. On the paging performance of array algorithms. IEEE Transactions on Computers, C- 26(10):938 947, October 1977.


Automatic Compiler-Inserted I/O Prefetching for.. - Mowry, Demke, Krieger (1996)   (43 citations)  (Correct)

....Using application specific knowledge to assist memory management policies was studied by Malkawi and Patel [18] however they only considered retaining needed pages in memory and did not consider prefetching. The most relevant work to our study was conducted nearly twenty years ago by Trivedi [32], who looked at the use application access patterns extracted by a compiler to implement prepaging . Although the interface to the OS is nearly identical, there are some significant di#erences. First, Trivedi s compiler analysis was restricted to programs in which blocking could be performed ....

K.S. Trivedi. On the paging performance of array algorithms. IEEE Transactions on Computers, C26 (10):938--947, October 1977.


Compilation and Communication Strategies for Out-of-core.. - Bordawekar, Choudhary (1996)   (3 citations)  (Correct)

....performance of sequential programs. Abu Sufah in 1979 demonstrated the application of loop distribution and loop fusion for improving the memory access costs of numerical problems [AS79] while Trivedi showed that opportunities for demand prefetching can be identified from a program s syntax [Tri77] Another important area of investigation was use of iteration tiling for exploiting hierarchical memory [IT88, SD90, RS92] Several researchers have analyzed communication patterns in parallel programs. Important work in this area includes [GMG 88, LC91, Gup92, HKT92] There has been a lot ....

Kishor S. Trivedi. On the Paging Performance of Array Algorithms. IEEE Transactions on Computers, C-26(10):938--947, October 1977. 32


A Model and Compilation Strategy for Out-of-Core Data.. - Rajesh Bordawekar Alok (1995)   (18 citations)  (Correct)

....[FHK 90] Previous work on compiler improvements at the memory to disk interface starts with Abu Sufah and Trivedi at the end of the 1970 s. Abu Sufah [AS79] demonstrates that applying loop distribution and loop fusion can reduce the space time costs for numerical algorithms. Trivedi [Tri77a, Tri77b] shows that profitable opportunities for demand prefetching can be identified from a program s syntax. Highlights of managing other aspects of the memory hierarchy include: Allen and Kennedy on vector register allocation [AK87] Carr and Kennedy on compiler blocking of scientific codes [CK92] ....

K. S. Trivedi. On the paging performance of array algorithms. IEEE Transactions on Computers, C26 (10):938--947, October 1977.


Compilation Techniques for Out-of-Core Parallel Computations - Kandemir Choudhary.. (1998)   (3 citations)  (Correct)

.... on this line generally fall into two groups: 1) techniques which consider smart virtual memory implementations and replacement policies [2, 11] and (2) techniques which consider re shaping the data reference patterns in order to exploit the given hardware facilities and system software [23, 32]. The latter group then paved the way for automatic program restructuring techniques like loop distribution and page indexing [1] In general, these techniques apply to already written programs and consist of re arranging the code and data to make program s access pattern more local. Another ....

K. S. Trivedi. On the Paging Performance of Array Algorithms. IEEE Transactions on Computers, C-26(10):938947, October 1977.


Automatic I/O Prefetching for Out-of-Core Applications - Demke (1997)   (Correct)

....at each of these areas in turn. The idea of using a compiler to extract access patterns from an application and passing this information to the operating system to improve virtual memory performance is not a new one. The first study in this area was conducted nearly twenty years ago by Trivedi [33], who looked at the use of application access patterns extracted by a compiler to implement prepaging . Although the interface between the compiler and the operating system is nearly identical to that which we propose, there are some significant differences. First, Trivedi s compiler analysis was ....

K.S. Trivedi. On the paging performance of array algorithms. IEEE Transactions on Computers, C-26(10):938--947, October 1977.


Numerical Linear Algebra and Computer Architecture: An Evolving.. - Hedayat (1993)   (2 citations)  (Correct)

....elimination on the submatrix block. Would other methods on the blocks be preferable 6. 2 Block Algorithms The idea of block algorithms for linear algebra on machines with paged virtual store was addressed again in the 1960 s and 1970 s in the works of McKellar and Coffman [104] Trivedi [138], and Du Croz et al. 50] The interest and activity in developing block algorithms was increased sharply with the appearance of high performance multiprocessors containing a hierarchy of memory. Block algorithms rely on accessing large submatrices between different levels of memory. Agarwal and ....

Trivedi K., On the paging performance of array algorithms, IEEE Trans. Computer, C-26, 1977.


A Model and Compilation Strategy for Out-of-Core Data Parallel.. - Bordawekar (1995)   (18 citations)  (Correct)

....[FHK 90] Previous work on compiler improvements at the memory to disk interface starts with Abu Sufah and Trivedi at the end of the 1970 s. Abu Sufah [AS79] demonstrates that applying loop distribution and loop fusion can reduce the space time costs for numerical algorithms. Trivedi [Tri77a, Tri77b] shows that profitable opportunities for demand prefetching can be identified from a program s syntax. Highlights of managing other aspects of the memory hierarchy include: Allen and Kennedy on vector register allocation [AK87] Carr and Kennedy on compiler blocking of scientific codes [CK92] ....

K. S. Trivedi. On the paging performance of array algorithms. IEEE Transactions on Computers, C-26(10):938--947, October 1977.


Genetic Algorithms and Cache Replacement Policy - Altman, Agarwal, Gao (1992)   (2 citations)  (Correct)

.... : 10 2 Miss Rates for six small benchmarks and 3 replacement policies : 11 3 Number of Family Members examined by Genetic Algorithm to find optimum : 16 ii 1 Introduction There have been many investigations of the performance of different cache replacement policies [23, 6, 10, 13, 17, 24, 25, 11, 20, 28]. These have found that LRU generally performs significantly (10 ) better than FIFO or Random replacement [23] For an exception, see [25] Innovative variants have been suggested, for example Shadow Cache [20] and more recently, GODS [11] As well, adaptive caching policies such as FIDO [18] ....

Kishor S. Trivedi. On the paging performance of array algorithms. IEEE Transactions on Computers, 26(10):938--947, October 1977.


Automatic Compiler-Inserted I/O Prefetching for.. - Mowry, Demke, Krieger (1996)   (43 citations)  (Correct)

....Using application specific knowledge to assist memory management policies was studied by Malkawi and Patel [18] however they only considered retaining needed pages in memory and did not consider prefetching. The most relevant work to our study was conducted nearly twenty years ago by Trivedi [32], who looked at the use application access patterns extracted by a compiler to implement prepaging . Although the interface to the OS is nearly identical, there are some significant differences. First, Trivedi s compiler analysis was restricted to programs in which blocking could be performed ....

K.S. Trivedi. On the paging performance of array algorithms. IEEE Transactions on Computers, C26 (10):938--947, October 1977.


USENIX Association - General Track Usenix (1992)   (2 citations)  (Correct)

No context found.

K. S. Trivedi. On the paging performance of array algorithms. IEEE Transactions on Computers, 26(10):93 -- 947, 1977.


Operating System I/O Speculation: How two invocations are.. - Fraser, Chang   (Correct)

No context found.

K. S. Trivedi. On the paging performance of array algorithms. IEEE Transactions on Computers, 26(10):938-947, 1977.


USENIX Association - General Track Usenix (1992)   (2 citations)  (Correct)

No context found.

K. S. Trivedi. On the paging performance of array algorithms. IEEE Transactions on Computers, 26(10):93 -- 947, 1977.

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