D. T. Hoang and D. P. Lopresti, "FPGA Implementations of Systolic Sequence Alignment", in Field Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Springer-Verlag LNCS 705, 1993.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....across the available FPGAs and used VHDL to capture the behavior of each chip individually. Synthesis, followed by standard place and route, was used to do the final mapping. The second generation SPLASH achieved a speedup of more than 40,000X over a SPARC 1 on the genome sequencing problem [H93]. These speeds are obtained because the overall organization is carefully constrained by the designer, similar to the manual design systems already discussed. 4.4 What Works Best What works best would depend upon the user s requirements. However, it is important to remember that the primary ....

D. T. Hoang and D. P. Lopresti, "FPGA Implementations of Systolic Sequence Alignment", in Field Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Springer-Verlag LNCS 705, 1993.

....P NAC implementation, the bidirectional systolic array has been ported to the Splash programmable logic array [5] and now the Splash 2 programmable logic array. An extension of the bidirectional array to compute the alignment of two sequences in addition to the edit distance is described in [8,9]. Comparing sequences of lengths m and n requires at least 2 max(m 1; n 1) processors. The number of steps required to compute the edit distance is proportional to the length of the array. In a typical database search, the same source sequence is compared against all sequences in the database. ....

D. T. Hoang and D. P. Lopresti, "FPGA Implementation of Systolic Sequence Alignment," presented at 1992 International Workshop on Field Programmable Logic, Vienna, Austria, August 1992.

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