D. P. Lopresti. Rapid implementation of a genetic sequence comparator using FPGAs. Adv. Res. VLSI, pages 139--152, 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... hashing [ Digit recurrence division, square root [100, 99] Various (big num, algebra, 23 etc) 16] Polynomial evaluations [44] On line arithmetic [160] Floating point arithmetic [46] CORDIC [6, 104] Character recognition [164] DSP [30, 13, 118, 93, 106] Genome sequence matching [94, 98]. Engineering, sciences applications [16] 24 1964 1998 FPGA DPGA PRISC FPIC 66 72 68 70 74 78 76 82 80 84 86 88 90 92 96 94 Chimaera GARP GAMA PAM Xilinx XC6200 PRISM SPLASH CPS Estrin s m c TRIPTYCH DISC MATRIX RAW RaPiD CVH PAMBlox Spyder Figure 3.1: Reconfigurable ....

D. P. Lopresti. Rapid implementation of a genetic sequence comparator using FPGAs. Adv. Res. VLSI, pages 139--152, 1991.

....dealt with in subsequent sections of this survey. From Figure 3.1, it is clear that as a field, reconfigurable computing is rather new, but it is gaining momentum. 3. 2 Application Studies Wireless communications, spread spectrum communications,IQ demodulation [102, 142, 82] Genetic Algorithms [54, 68, 151, 97, 56, 55]. SAR,ATR [127, 130, 126, 167] Image coding, compression [147, 49, 142, 1, 16, 170, 134, 37, 41, 18] DCT,FFT,filters [148, 35, 176, 115, 81, 116, 146, 89] Viterbi decoder [180] Parallel object recognition, geometric hashing [ Digit recurrence division, square root [100, 99] Various ....

D. P. Lopresti. Rapid implementation of a genetic sequence comparator using field-programmable gate arrays. In C. Sequin, editor, Advanced Research in VLSI: Proceedings of the 1991 University of California/Santa Cruz Conference, pages 138--152, Santa Cruz, CA, March 1991.

.... rather than bit oriented; thus it is not surprising that many of the applications in which these systems excell involve many bit level operations, with notable examples including automatic target recognition [56, 68] cryptography [60, 65] scientific computations [52] genetic algorithms [29, 45], genome sequencing [70] image processing [5, 22, 57, 59, 73] signal processing [9, 17, 18, 27, 41, 51, 55, 58] and artificial neural networks [19, 24, 47] A number of development environments have been constructed, with the Trianus Lola system [28] being of particular interest. It provides ....

D. P. Lopresti, Rapid implementation of a genetic sequence comparator using field-programmable gate arrays, in Advanced Research in VLSI: Proceedings of the 1991 University of California/Santa Cruz Conference, C. Sequin, ed., Santa Cruz, CA, Mar. 1991, pp. 138--152.

....assignment tool simply requires permanently locking these signals into their proper locations. Experimental Results To compare the various pin assignment approaches, we tested each approach on mappings for four different current systems. These include a systolic DNA comparison circuit for Splash [15], a telecommunications circuit for the NTT board [23] a calorimeter circuit for DECPeRLe 1 [21] and a RISC processor configured for logic simulation on the Marc 1 system [14] The pin assignment systems compared are: Random , which randomly assigns connections to traces; Checkerboard and ....

....a reasonable approximation of the routing resource usage of the different systems. 18 RAM RAM RAM RAM 17 16 18 15 31 2 32 1 FIFO IN FIFO OUT RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM A B C D E F G H I J K L M N O P Q U R S V T W Host Interface Figure 8. The SPLASH system [15] (left) and the DECPeRLe 1 board [21] right) The Splash system [8] is a linear array of Xilinx 3090 FPGAs (Figure 8 left) with memories attached to some of the communication wires. As expected, Random does poorly on the average wirelength, with Checkerboard and Wavefront each doing ....

D. P. Lopresti, "Rapid Implementation of a Genetic Sequence Comparator Using FieldProgrammable Logic Arrays", Advanced Research in VLSI 1991: Santa Cruz, pp. 139-152, 1991.

....far beyond what was expected. Scientists have exploited the reprogrammability of these devices to build custom hardware to solve computationally intensive problems such as simulation of spin systems in statistical physics [21] calculation of evolutionary distance between gene sequences [22, 23, 24], and real time image segmentation on an assembly line [19] Reprogrammable FPGAs also form the basis of both hardware emulation [25, 26, 27] and new approaches to system level reconfigurability [25, 28, 29] In particular, GANGLION [19] is a connectionist classifier (a.k.a. artificial neural ....

Daniel P. Lopresti. Rapid implementation of a genetic sequence comparator using fieldprogrammable logic arrays. In Advanced Research in VLSI, Proceedings of the 1991 UC Santa Cruz Conference, pages 138--152, Santa Cruz, CA, 1991.

....use of reconfigurable logic to obtain substantial speedup in the case of large regular binary operations. DEC Paris s PAM (Programmable Active Memories) is an array of Xilinx FPGAs attached to a host work station [3] The Super computing Research Center in Maryland has built a system called SPLASH [4]. SPLASH has been used to speed up genome sequence matching applications. We find that the existing literature does not analyze the effect of processor programmable logic interface on the performance of the system. Further, if we add new instructions to a pipelined processor, the interactions ....

D.Lopresti, Rapid Implementation of a Genetic Sequence Comparator using Field-Programmable Logic Arrays, Advanced Research in VLSI, April 1991, pp 138-152.

....the edit distance between two strings. The edit distance is the minimum number of insertions and deletions necessary to transform one string into another, so the strings flea and fleet would have an edit distance of 3 (delete a and insert et to go from flea to fleet ) As shown in [Lopresti91] a dynamic programming solution to this problem can be implemented in the Splash system as a linear systolic circuit, with the strings to be compared flowing in opposite directions through the linear array. Processing can occur throughout the linear array simultaneously, with only local ....

.... Problem [Graham95] Monte Carlo yield modeling [Howard94b] genetic optimization algorithms [Scott95, Graham96] region detection and labeling [Rachakonda95] stereo matching for stereo vision [Vuillemin96] hidden Markov Modeling for speech recognition [Schmit95] and genetic database searches [Lopresti91, Hoang93, Lemoine95] One of the most successful uses for FPGA based computation is in ASIC logic emulation. The idea is that the designers of a custom ASIC need to make sure that the circuit they designed correctly implements the desired computation. Software simulation can perform these ....

D. P. Lopresti, "Rapid Implementation of a Genetic Sequence Comparator Using Field-Programmable Logic Arrays", Advanced Research in VLSI 1991: Santa Cruz, pp. 139-152, 1991.

....Laboratory of Mathematical Biology in Fredrick, Maryland. The goal was to develop sequence comparison algorithms for the SPLASH programmable logic array. A systolic sequence comparison algorithm that computes the edit distance between a pair of sequences had already been implemented on SPLASH [1]. Certain applications of interest to biologists at the laboratory, such as multiple alignment of genetic (DNA and RNA) sequences, however, require more than just the edit distance: a more informative analysis of the similarity, or homology, of the sequences in the form of an alignment is ....

....arrays for both phases exist in SPLASH concurrently and their operations are controlled by a FSM controller. We discuss both arrays and the controller below in separate sections. 6. 1 Phase One: Sequence Comparison The phase one array is basically the sequence comparison design described in [1] modified to store the computed DP distances in local RAM. Figure 17 shows a block diagram of the sequence comparison PE. The SPLASH implementation uses 13 CLB s per PE, eight for the character comparator and five for the finite state machine. The character comparator contains registers to store a ....

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D. P. Lopresti, "Rapid Implementation of a Genetic Sequence Comparator Using FieldProgrammable Logic Arrays," Invited paper, Advanced Research in VLSI Conference, March 1991, Santa Cruz, CA.

....Quinton 3.4 La machine Splash 2 La machine Splash 2 [2] concue au Src (Supercomputing Research Center Institut for Defense Analyses) pr esente d int eressantes possibilit es. C est egalement un syst eme a base de circuits programmables (Fpga) Elle est le successeur de la machine Splash 1 [13] initialement etudi ee pour des applications en biologie mol eculaire. Splash 2 est un r eseau lin eaire dont chaque noeud est compos e d un Fpga (Xilinx 4010, l equivalent de 10 000 portes logiques) et d une m emoire statique de 512 Ko. La configuration maximum est de 256 noeuds repartis sur 16 ....

Daniel Lopresti. Rapid Implementation of a Genetic Sequence Comparator Using FPGAs. Advance Research in VLSI 1991, 139--152, 1991.

....XILINX 4010 16 20 36 36 36 X Processing Element 36 Figure 2.2: SRC SPLASH 2 listed in Table 2.2. Again, these applications all demonstrate performance improvements by specializing a computing architecture for each problem of interest. ffl Text searching [42] ffl Genetic database searching [43, 14] ffl Image processing [44, 45, 17] ffl 2 D convolution [46] ffl Custom floating point [47] ffl Genetic algorithms [48] ffl Automatic target recognition [49] Table 2.2: SPLASH Applications. The PeRLe and SPLASH architectures successfully demonstrate that a single CCM platform can achieve ....

....the most impressive improvements in performance all exploit massive concurrency. For example, the genetic sequencing application mapped onto the SPLASH I platform achieves a speedup of 325 over a CM 2 supercomputer by allowing 746 special purpose processing 15 elements to operate concurrently [43]. In addition, the long multiplication acceleration library developed for the DEC PeRLe architecture demonstrates a multiplication rate faster than any known machine of its time. It accomplishes this by replicating a large set of digit serial multiplication processors [30] 2.2.3 Optimized ....

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D. P. Lopresti. Rapid implementation of a genetic sequence comparator using field-programmable gate arrays. In C. Sequin, editor, Advanced Research in VLSI: Proceedings of the 1991 University of California/Santa Cruz Conference, pages 138--152, Santa Cruz, CA, March 1991.

....executes. A source code debugger has been implemented for this system. 1 Introduction FPGAs are capable of achieving high performance on many application specific tasks. In many cases performance achievable with FPGAs on certain applications exceeds comparable ASIC designs or even super computers[2, 7]. One approach used in obtaining this high performance on application specific designs is through a framework of application specific modules and a programmable core like the DISC[12] processor. The programmable core is functionally capable of supporting high level languages like ANSI C. The ....

D. P. Lopresti. Rapid implementation of a genetic sequence comparator using field-programmable gate arrays. In C. Sequin, editor, Advanced Research in VLSI: Proceedings of the 1991 University of California/Santa Cruz Conference, pages 138-- 152, Santa Cruz, CA, March 1991.

....on Splash II with impressive results [5] This application implements a well known dynamic programming algorithm to compute the edit distance, a measure of similarity, between genetic sequences. The Princeton Nucleic Acid Comparator(PNAC) VLSI chip for this algorithm has been ported to Splash I [6]. By pre storing the source sequence into the system before operation, a new implementation written in VHDL improved PE utilization of the algorithm to near 100 . Packing 14 PEs into a single FPGA, a complete Splash system with 16 boards contains 3608 PEs. Peak performance of the system is ....

D. P. Lopresti. Rapid implementation of a genetic sequence comparator using field-programmable gate arrays. In C. Sequin, editor, Advanced Research in VLSI: Proceedings of the 1991 University of California/Santa Cruz Conference, pages 138--152, Santa Cruz, CA, March 1991.

....FPGA capabilities. Any irregularity in the FPGA s basic structure can also impair automatic place and route efficiency. FPGAs have been used to build a variety of platforms. Many of these platforms have shown significant performance advantages over high performance systems and supercomputers [9, 12, 17, 19]. Other applications implemented on FPGAs show the value of a flexible, reconfigurable platform [20, 25] However, FPGA based systems have not been shown to be a good alternative for all computing applications and in some cases have shown significant cost and performance disadvantages [2] 1.3 ....

D. P. Lopresti. Rapid implementation of a genetic sequence comparator using field-programmable gate arrays. In C. Sequin, editor, Advanced Research in VLSI: Proceedings of the 1991 University of California/Santa Cruz Conference, pages 138--152, Santa Cruz, CA, March 1991.

....The configuration of the FPGA does not change during the execution of the algorithm. It is only reconfigured at the start of an algorithm s execution and the configuration is modified only if it is necessary to execute another 4 Eldredge and Hutchings algorithm. Splash [1] 32] 2] 23] 3] [26], the PRISM work at Brown University [4] 37] 36] and the Programmable Active Memory (PAM) work at DEC Paris labs [6] are well known examples of this approach. FPGAs have also been used to implement application specific processors as described in [39] 24] 29] Several industrial ....

D. P. Lopresti. Rapid implementation of a genetic sequence comparator using field-programmable gate arrays. In C. Sequin, editor, Advanced Research in VLSI: Proceedings of the 1991 University of California/Santa Cruz Conference, pages 138--152, Santa Cruz, CA, March 1991.

....in FPGA based computing machines have been mixed. The research has produced several reported successes where FPGAbased custom computers have been able to outperform supercomputers and other high performance programmable processor machines despite the speed limitations of the FPGAs themselves [Lop91] BRV93] MVB95] WCS96] Also, as might be expected, many FPGA based custom computing solutions are not orders of magnitude faster than or even as fast as their programmable processor counterparts when employed in some applications because of the speed and logic density limitations of current ....

....solutions. The development time for CCM applications generally lies in between that of custom hardware and software. Though not able to operate at the clock rates of today s programmable computers, some CCMs have been found to outperform even supercomputers in a number of applications [BRV93] Lop91] because of the specialization and parallelism exploited in the hardware designs, as mentioned earlier. A challenge for the community creating CCMs has been to understand what CCM architectures make sense for certain algorithms as well as what algorithms make sense for certain CCM architectures. ....

D. P. Lopresti. Rapid implementation of a genetic sequence comparator using field-programmable gate arrays. In C. Sequin, editor, Advanced Research in VLSI: Proceedings of the 1991 University of California /Santa Cruz Conference, pages 138--152, Santa Cruz, CA, March 1991.

....wide range of algorithms. In some cases, classes of algorithms not previously suitable for ASIC realization can now benefit from hardware implementation on these machines. Splash 2 and PAM applications have been shown to often run orders of magnitude faster than equivalent software implementations[4][5] In this work we describe the result of mapping a genetic algorithm for solving the traveling salesman problem onto the Splash 2 system. We demonstrate the This work was supported by ARPA CSTO under contract number DABT63 94 C 0085 under a subcontract to National Semiconductor ....

D. P. Lopresti. Rapid implementation of a genetic sequence comparator using field-programmable gate arrays. In C. Sequin, editor, Advanced Research in VLSI: Proceedings of the 1991 University of California/Santa Cruz Conference, pages 138--152, Santa Cruz, CA, March 1991.

....Center has built a series of programmable systolic arrays known as SPLASH [18] 7] Each SPLASH array attaches to a host workstations and is composed from a number of Xilinx FPGAs in an array fashion along with support memory. SPLASH has seen heavy use in genome sequence matching applications [16]. ffl DEC Paris s PAM (Programmable Active Memories) is an array of Xilinx FPGAs attached to a host workstation [5] The DEC team has demonstrated significant performance improvements on many applications by appropriate specialization of the PAM accelerator. ffl Algotronix s CH2x4 provides a ....

....to extract high performance [20] 4] 4. Sequence and string matching By recognizing the application s natural structure and specializing a configurable compute engine to take advantage of the structure, researchers have managed to achieve very high performance at modest costs [14] 12] [16]. 5. Sorting Sorting tasks exhibit natural, fine grained parallelism. By exploiting this parallelism, large sorting tasks can be performed efficiently with sorting networks built from configurable logic [17] 6. Physical system simulation Simulating physical phenomena often require repeated ....

Daniel Lopresti. Rapid Implementation of a Genetic Sequence Comparator Using Field-Programmable Logic Arrays. In Carlo H. S equin, editor, Advanced Research in VLSI, pages 138--152, Cambridge, MA, April 1991. MIT Press.

....to c.h. 79 A.8 Changes to dag.c and simp.c. 79 x Chapter 1 INTRODUCTION FPGAs have demonstrated their effectiveness on a variety of tasks, in many cases outperforming super computers and ASICs[3, 6, 20, 31]. One approach used in obtaining this high performance on applicationspecific designs is through a framework of application specific modules and a programmable core like the DISC[32] processor. The programmable core is functionally capable of supporting high level languages like ANSI C. The ....

....the logic configuration. FPGAs are excellent prototyping devices and may be rapidly reprogrammed[11] typically less than a second) to implement an entirely different algorithm. They have proved effective in implementing image processing, digital signal processing[19] genetic database search[20] and custom computing[1] algorithms. They are used frequently as commercial products[18] in the short design cycle, low volume custom VLSI market. This chapter will give an overview of SRAM based FPGA architectures and the DISC architecture. It discusses some general architectural features of the ....

D. P. Lopresti. Rapid implementation of a genetic sequence comparator using field-programmable gate arrays. In C. Sequin, editor, Advanced Research in VLSI: Proceedings of the 1991 University of California/Santa Cruz Conference, pages 138--152, Santa Cruz, CA, March 1991.

....[3] In this report, we describe two systolic arrays for computing the edit distance and their implementations on the Splash 2 programmable logic array. One of the systolic arrays was previously implemented on P NAC [4] a special purpose VLSI chip, and later ported to the original Splash hardware [5]. The second systolic array is an improvement on the first for database search applications. 1 Release 74.0 of GenBank, a database of DNA sequences, contains 97,084 entries with a total of 120,242,234 bases as of December 1992. It is estimated that by 1999, 1.6 billion base pairs will be ....

....one of antidiagonals of the distance matrix. At the end of the computation, the resulting edit distance is transported out of the array on the distance streams. In addition to the original P NAC implementation, the bidirectional systolic array has been ported to the Splash programmable logic array [5] and now the Splash 2 programmable logic array. An extension of the bidirectional array to compute the alignment of two sequences in addition to the edit distance is described in [8,9] Comparing sequences of lengths m and n requires at least 2 max(m 1; n 1) processors. The number of steps ....

D. P. Lopresti, "Rapid Implementation of a Genetic Sequence Comparator Using Field-Programmable Logic Arrays," presented at Advanced Research in VLSI Conference, Santa Cruz, March 1991, Invited paper.

....of Mathematical Biology in Fredrick, Maryland. The goal was to develop genetic sequence analysis algorithms for the SPLASH reconfigurable logic array [3] A systolic sequence comparison algorithm that computes the edit distance between a pair of sequences had already been implemented on SPLASH [4]. Certain applications of interest to biologists at the laboratory, such as multiple alignment of genetic (DNA and RNA) sequences, however, require more than just the edit distance: a more informative analysis of the similarity, or homology, of the sequences in the form of an alignment is ....

....recurrence can be mapped onto a linear systolic array that computes a single antidiagonal of the dynamic programming table at each step, with each PE in the array computing the distances along one diagonal. The resulting systolic array (Figure 2) and its implementation on SPLASH is described in [4]. The array is modified to save the dynamic programming table in local RAM. The first phase ends just after the edit distance, d m;n , has been computed. Figure 3 shows a block diagram of a sequence comparison PE. Each PE is implemented in 13 CLB s, eight for the character comparator and five for ....

[Article contains additional citation context not shown here]

D. P. Lopresti, "Rapid Implementation of a Genetic Sequence Comparator Using Field-Programmable Logic Arrays," presented at Advanced Research in VLSI Conference, Santa Cruz, March 1991, Invited paper.

....with the present SPLASH system. It had been hoped that developers coming from a software background could learn to program SPLASH, but this has not been the case. Myriad hardware level details must be mastered, including issues in routability, clocking, and the crossing of chip boundaries [Lopr91]. Many of these stem from the Xilinx 3090 not being designed with this specific purpose in mind. To address these concerns, a highly simplified spreadsheet model called POOL was proposed [Lipt89] In POOL, each CLB is limited to reading inputs from its neighbors to the north and west, and writing ....

D. P. Lopresti, "Rapid Implementation of a Genetic Sequence Comparator Using Field- Programmable Logic Arrays," to be presented at the 1991 Conference on Advanced Research in VLSI, Santa Cruz, CA, March 1991.

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D. P. Lopresti. Rapid implementation of a genetic sequence comparator using FPGAs. Adv. Res. VLSI, pages 139--152, 1991.

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D. P. Lopresti. Rapid implementation of a genetic sequence comparator using field-programmable gate arrays. In C. Sequin, editor, Advanced Research in VLSI: Proceedings of the 1991.

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D. P. Lopresti, "Rapid Implementation of a Genetic Sequence Comparator Using Field-Programmable Logic Arrays", Advanced Research in VLSI 1991: Santa Cruz, pp. 139-152, 1991.

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D. P. Lopresti, "Rapid Implementation of a Genetic Sequence Comparator Using Field-Programmable Logic Arrays", Advanced Research in VLSI 1991: Santa Cruz, pp. 139-152, 1991.

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D. P. Lopresti, "Rapid Implementation of a Genetic Sequence Comparator Using Field-Programmable Logic Arrays", Advanced Research in VLSI 1991: Santa Cruz, pp. 139-152, 1991.

No context found.

D. P. Lopresti, "Rapid Implementation of a Genetic Sequence Comparator Using Field-Programmable Logic Arrays", Advanced Research in VLSI 1991: Santa Cruz, pp. 139-152, 1991.

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