H. Li and M. Maresca, "Polymorphic-Torus Architecture for Computer Vision," IEEE Trans. Pattern Analysis and Machine Intelligence, vol. 11, no. 3, pp. 233-243, Mar. 1989.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....structure in it. Second, we derive a constant time parallel algorithm to solve this problem on the reconfigurable array of processors with wider bus networks (RAPWBN) The system bus bandwidth determines the capacity of data communication between processors. According to the results as shown in [15], 17] we know that the silicon area used by the switching control mechanism is far less than that used by the processor. Instead of increasing the number of processors, we extend the number of buses to increase the power of a parallel processing system. Such a strategy of utilizing the ....

....it with a reconfigurable bus system. Several reconfigurable parallel processing systems have been proposed [6] 10] 16] 18] 19] 26] 27] 30] 31] There are processor arrays with a reconfigurable bus system (PARBS) 30] 31] reconfigurable mesh [18] 19] polymorphic torus network [15], bus automation [26] reconfigurable array of processors [7] reconfigurable network [27] and polymorphic processor arrays [16] Although the system bus of any reconfigurable parallel processing system is reconfigurable at run time, there is still a drawback to these models; that is, the ....

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H. Li and M. Maresca, "Polymorphic-torus architecture for computer vision," IEEE Trans. Pattern Anal. Machine Intell., vol. 11, pp. 233--243, Mar. 1989.

....using a store and forward scheme while others might use wormhole routing. 6. Recently proposed architectures that use reconfigurable electronic and optical buses use the interconnection network to perform tasks that can be done only by processor computation in other parallel architectures [5] [25], 28] 37] 46] and [47] The simplest and oldest of the parallel computer models is the PRAM. This simply extends the RAM model by permitting several processors to share the same memory. The PRAM model is a synchronous shared memory model (SMM) Since it makes no provision for the stated ....

H. Li and M. Maresca, Polymorphic-torus architecture for computer vision, IEEE Trans. on Pattern Machine Intelligence,

.... is considered by Ibrahim et al. IBRA86] Rather than deal in (r,q) space, their work uses the (m,c) space where m is the slope and c is the y axis intercept of the line (i.e. the straight line equation y = mx c is used) A Hough transform algorithm for a polymorphic torus is developed in [LI89, MARE88, and MARE89] and a fast Hough transorm algorithm is given in [LI86] In this paper we consider a variant of the mesh connected computer. This variant called reconfigurable mesh with buses (RMESH) was introduced by Miller, Prasanna Kumar, Resis, and Stout [MILL88abc] We develop algorithms to compute the p ....

Li, and Maresca, "Polymorphic-torus architecture for computer vision", IEEE Trans. on PAMI, 11, 3, March 1989.

....tures. Chaung and Li [2] and Li et a . 23] do this for systolic arrays; Rosenreid et a . 34] Kannan and Chaung [17] Cypher et a . 4] Guerra and Hambrusch [8] and Silberberg [37] consider mesh computers; Fisher and Highham [6] use a scan line array; Ibrahim et a . 10] uses a SIMD tree; Li et a . [21, 22], Maresca et a . 25] use a polymorphic torus; Ranka and Sahni [32] use hypercube computers; Choudhary and Ponnusamy [3] and Thazhuthaveetil and Shah [39] use shared memory multiprocessors; Jenq and Sahni [14] and Olariu et a . 29] use reconfigurable meshes; and Pavel and Akl [30] use optical ....

H. Li and Maresca. Polymorphic-torus architecture for computer vision. IEEE Transactions on Pattern Analysis and Machine Intelligence, 11(3), Mar. 1989.

....segments. We use the notation DMBC(p, b, io) to denote a DMBC with p processors, b buses, and io I O ports lines per processor. Architecturally, the DMBC is also closely related to the reconfigurable networks of Ben Asher et al. 1] and the various reconfigurable mesh architectures proposed in [6, 8, 9, 10, 12, 13, 14, 22]. A DMBC(n, 1, 1) for example, is identical to a one dimensional RMESH, PARBUS, and MRN (see [17] for example, for a definition of these variants of a reconfigurable mesh) A DMBC(n,m, 1) may be viewed as a generalization of a one dimensional RMESH to the case of multiple buses and a DMBC(n, n, ....

H. Li and M. Maresca, Polymorphic-torus architecture for computer vision, IEEE Trans. on Pattern 4 Machine Intelligence, 11, 3, 133-143, 1989.

....implementation by interconnection networks is quite suitable [1, 3] Unfortunately, both fixed architecture and locality communication mechanism are two inherent drawbacks of the mesh connected computer. Researchers overcame these two drawbacks by equipping it with a reconfigurable bus system [4, 6, 8 11, 14]. A reconfigurable parallel processing system can be defined to be a set of processors connected to a reconfigurable bus system whose configuration can be dynamically established at run time. There are several varieties of this kind of machine including the reconfigurable meshes [6, 10, 11] the ....

....system can be defined to be a set of processors connected to a reconfigurable bus system whose configuration can be dynamically established at run time. There are several varieties of this kind of machine including the reconfigurable meshes [6, 10, 11] the polymorphic torus architecture [8, 9], the processor array with a reconfigurable bus system [14] and the reconfigurable array of processors [4] A major difference among these proposed models lies in howmany connection patterns are allowed within each processor. Due to the reconfigurability of the bus system, many problems can be ....

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H. Li and M. Maresca, Polymorphic-torus architecture for computer vision, IEEE Trans. Pattern Anal. Mach. Intelligence 11, 1989, 233--243.

....processing system can be defined to be a set of processors connected to a reconfigurable bus system whose configuration can be dynamically established at run time. There are lots of varieties of this kind of machine including the reconfigurable meshes [16] the polymorphic torus architecture [14,15], the processor array with a reconfigurable bus system [21] and the reconfigurable array of processors [9,11] As a result of the reconfigurability of the bus system, many problems can be solved in constant time on such a machine. Based upon the proposed models, a VLSI clip, called YUPPIE ....

....system [21] and the reconfigurable array of processors [9,11] As a result of the reconfigurability of the bus system, many problems can be solved in constant time on such a machine. Based upon the proposed models, a VLSI clip, called YUPPIE (Yorktown Ultra Parallel Polymorphic Image Engine) [14,15], has been practically fabricated to prove these models being implementable. The more processors are used in the system, the better executing time of an algorithm can be probably reached. In fact, the running time of an algorithm can be also improved by using the wider bus system instead of using ....

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H. Li, M. Maresca, Polymorphic-torus architecture for computer vision, IEEE Trans. on Patt. Analys. and Machine Intell. 11 (1989) 233--243.

....product was produced by MasPar (Blank 1990) and recently upgraded to the MP 2 (Tuck Kim 1993) There are also several research designs which have not been put into commercial production. These designs explored different aspects of SIMD architectures. For example, IBM s polymorphic torus (Li Maresca 1989) concentrated on adding connection autonomy by the addition of locally reconfigurable network switches. The MCNC Blitzen project (Blevins, Davis, Heaton Reif 1988) updated the original MPP design for VLSI technology by adding on chip RAM, local modification of addresses, and an X grid 8 neighbor ....

Li, H. & Maresca, M. (1989), `Polymorphic-Torus Architecture for Computer Vision', IEEE Trans. Pattern Analysis and Machine Intellegence 11(3), 233--243.

....conditionnelles, l interconnexion avec huit voisins. Le circuit integre 128 processeurs (tableau 8 x 16) et comprend plus d un million de transistors, chaque processeur dispose d une memoire locale de 1K bits. 2. 3 Tore polymorphique (IBM, universit e de G enes) Le Tore polymorphique (1987) [LiMa89] constitue une etude interessante de re seau bidimensionnel configurable. L architecture consiste en un reseau physique (PNET) comportant a chaque noeud un reseau interne programmable (INET) Une architecture a n x n processeurs est un grille n x n dont les extremites sont reliees en tore ou en ....

H. Li et M. Maresca. Polymorphic-Torus Architecture for Computer Vision. IEEE Transactions on Pattern Analysis and Machine Intelligence, 11(3):320--330, mars 1989.

....added to a number of parallel machines [1 6] If such a bus system can be dynamically changed, under program control, to suit communication needs among processors, it is referred to as reconfigurable. Examples include the bus automaton [6] the reconfigurable mesh [3,4] and the polymorphic torus [1,2]. The computational model used throughout this work is the reconfigurable mesh. 1 An m n reconfigurable mesh consists of m n identical processors positioned on a rectangular array (refer to Figure 1) The processor located at (i , j ) 0i m 1; 0j n 1) is referred to as P (i , j ) Every ....

H. Li and M. Maresca, "Polymorphic-torus architecture for computer vision," IEEE Trans. Pattern Analysis and Machine Intelligence, vol. 11, no. 3, pp. 233243, 1989.

.... Automata which is a cellular automata with a locally switchable global communication network [2] the reconfigurable meshes with buses (RMESH) 3, 4, 5, 6, 7, 8, 9, 10, 11] the CAAPP [12] the processor array with reconfigurable bus system (PARBS) 13, 14, 15, 16, 17, 11] the Polymorphic Torus [18, 19, 20, 21], and the reconfigurable network (RN) 22] The reconfigurable MCCs can efficiently simulate many architectures such as rings, trees, meshes with multiple broadcast buses, mesh of trees, and pyramids [3, 4, 6, 21] This paper classifies the reconfigurable interconnection meshes into two major ....

H. Li and M. Maresca. Polymorphic-torus architecture for computer vision. IEEE Transactions on Pattern Analysis and Machine Intelligence, 11(3):233--243, 1989.

....of processors [BEAM87] Furthermore, the O(1) time RMESH algorithm is fairly simple. Because of the power and ease of programming of this model, it is interesting to explore the potential application of this model to various application areas. Some initial work in this regard has already been done [LI89a, MILL88c, MILL91ab, JENQ91abc, WANG90ab]. In this paper, we consider most of the fundamental parallel processing data manipulation operations identified in [RANK90] and develop efficient RMESH algorithms for these. This should simplify the This research was supported in part by the National Science Foundation under ....

H. Li and M. Maresca, "Polymorphic-torus architecture for computer vision," IEEE Trans. on Pattern & Machine Intelligence, 11, 3, 133-143, 1989.

....to demonstrate the performance of the design in a certain application domain by coding some standard algorithms, running them, and determining the performance. Some machines and proposed machines that have been evaluated in this way are the Connection Machine [140, 141, 98] the Polymorphic Torus [93], the Mesh with Multiple Broadcast [118] and the Aspex ASP [89] This technique is most useful in providing proof of a basic concept. 20 2.2.5 Benchmarking A more systematic approach to evaluating existing machines and machine designs is by standardizing the above process through organized ....

....shaped contiguous broadcast buses. At least three varieties of broadcast networks have been, or are being, built. They are all based on the two dimensional mesh topology. Broadcast Buses [114, 113] PEs can broadcast receive data to from their own rows columns. 35 Reconfigurable Buses [93, 94]. These are the same as broadcast buses, with the added capability that PEs control switches to open circuit the bus in either direction on either bus, preventing the signal from propagating further. Coterie Network [147] The coterie network is also known as the reconfigurable mesh. It is ....

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Li, H., and Maresca, M. The Polymorphic-Torus Architecture for computer vision. IEEE Transactions on Pattern Analysis and Machine Intelligence PAMI-11, 3 (1989), 233--243. 177

....that meets those requirements, and provide algorithms for that hardware [29] In turn, algorithmic development inspires new types of hardware support, bringing to light new computational possibilities, influencing the way we think about machine vision. Similar research efforts can be found in [32, 21, 20, 26, 1] and others, with more or less emphasis on either the architecture or the vision end of the research. A common thread in these studies is that low level vision involves more than the window based operations that dominated earlier research. What makes our work unique is that our programming model ....

....read a register which will have been set to the OR of these signals, within a local group as defined by the network configuration. This scheme is a generalization of the flash through mode of the ILLIAC III [23] and the propagate operation in the CLIP 4 [8] and is similar to those proposed by [24, 20]. In order to distinguish broadcast by PEs from the usual broadcast by the controller, we refer to this operation as coterie multicast . The coterie network is one powerful addition that the CAAPP has over conventional associative processors. Each PE in the CAAPP controls a set of eight switches ....

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H. Li and M. Maresca (1989): "The Polymorphic-Torus Architecture for Computer Vision," IEEE Trans. on PAMI, PAMI-11 (3).

....Elizabeth City State University, Elizabeth City, NC 27909 system can be dynamically changed, under program control, to suit communication needs among processors, it is referred to as reconfigurable. Examples include the bus automaton [11,12] the reconfigurable mesh, and the polymorphic torus [2,3], among others. 1 6 2 5 3 4 Figure 1: A reconfigurable mesh of size 4 Theta 5 The computational model used throughout this work is the reconfigurable mesh [5] A reconfigurable mesh of size m Theta n consists of m Theta n identical processors positioned on a rectangular array as shown in Figure ....

H. Li and M. Maresca, Polymorphic-torus architecture for computer vision, IEEE Trans. Pattern Analysis and Machine Intelligence, vol. 11, no. 3, (1989) 233-243.

....processing. Most of them are SIMD processors like SYMPATI 2 [2] IMAP [25] SCAM [14] MGAP [13] or MasPar MP 1 [15] which obtain very good results on synchronous regular algorithms. Few MIMD dedicated processors have been developed such as IUA [26] PASM [27] SM IMP [28] or the Polymorphic Torus [29]. The general purpose GFLOPS computer is aimed at obtaining equivalent computing and communication power as the dedicated SIMD architectures. It is difficult to compare SIMD and MIMD architectures. GFLOPS is a cost effective solution because it is possible to obtain, with low cost PCs, the same ....

H. Li and M. Maresca (1989) The Polymorphic-Torus Architecture for Computer vision. IEEE Trans. on PAMI, pp. 233-243.

.... reconfigurable mesh [15] the mesh with bypass capability [8] the content addressable array processor [29] the reconfigurable network [2] the polymorphic processor array [13, 14] the reconfigurable bus with shift switching [11] the gated connection network [23, 24] and the polymorphic torus [9, 10]. Among these, the reconfigurable mesh has emerged as a very attractive and versatile architecture. In essence, a reconfigurable mesh (RM) consists of a mesh augmented by the addition of a dynamic bus system whose configuration changes in response to computational and communication needs. More ....

....a model that allows at most two connections to be set in each processor at any one time. Furthermore, these two connections must involve disjoint pairs of ports as illustrated in Figure 2. Some other models proposed in the literature allow more than two connections to be set in every processor [9, 10]. One of our results uses such a model. In accord with other workers [9, 10, 13 16, 21] we assume that communications along buses take O(1) time. Although inexact, recent experiments with the YUPPIE and the GCN reconfigurable multiprocessor system [16, 23, 24] seem to indicate that this is a ....

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H. Li and M. Maresca, Polymorphic-torus architecture for computer vision, IEEE Transactions on Pattern Analysis and Machine Intelligence, 11, (1989), 233--243.

....CHiP and consist of thousands of switches and processors. Suggested implementations are both electronic [X86, MKS89] and optic [TCS89, BS90a] A VLSI chip called YUPPIE (Yorktown Ultra Parallel Polymorphic Image Engine) has been implemented on a reconfigurable torus, also called polymorphic torus [LM89a, LM89b]. Another existing VLSI design is the CAL Chip, currently consisting of a 16 Theta 16 reconfigurable mesh of switches [GK89] 1.2 The Power of Reconfiguration Reconfigurable Networks outperform PRAM s in the computation of several natural problems. For example, consider the computation of the ....

H. Li and M. Maresca, Polymorphic-torus architecture for computer vision, IEEE Trans. Pattern Anal. Machine Intell., Vol. 11, No. 3, pp. 233--243, March 1989.

....operations per iteration and log N iterations. Other communication networks for which nonuniform region processing has been studied are mesh connected arrays [30, 32] and pyramid processors [22] Other work that has been done on vision computation using reconfigurable meshes can be found in [17, 27, 11]. The algorithms presented here use a very different approach than that normally used on a reconfigurable broadcast mesh: they are based on the concept of the coterie structure, first introduced in [11] Each region is processed using only those PEs to which the pixels of the region have been ....

H. Li and M. Maresca, "The Polymorphic-Torus Architecture for Computer Vision," IEEE Transactions on Pattern Anaylysis and Machine Intelligence, Volume PAMI-11, pp. 233-243, March, 1989.

.... include the bus automaton [36] the reconfigurable mesh [27] the mesh with bypass capability [15] the content addressable array processor [48] the reconfigurable network [4] the polymorhic processor array [24, 25] the reconfigurable bus with shift switching [23] and the polymorphic torus [21, 22]. Among these, the reconfigurable mesh has emerged as a very attractive and versatile architecture. The purpose of this paper is to show that a number of fundamental algorithmic problems that involve trees can be solved in constant time on reconfigurable meshes. To the best of our knowledge, ....

....1 2 3 4 5 1 2 3 4 Figure 2: Examples of allowed connections At any given time, only one processor can broadcast a value onto a bus. Processors, if instructed to do so, read the bus: if no value is being transmitted on the bus, the read operation has no result. In accord with other workers [21, 22, 24, 25, 26, 27, 36] we assume that communications along buses take O(1) time. Although inexact, recent experiments with the YUPPIE reconfigurable multiprocessor system [26] seem to indicate that this is a reasonable working hypothesis. We assume that the processing elements have a constant number of registers of ....

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H. Li and M. Maresca, Polymorphic-torus architecture for computer vision, IEEE Transactions on Pattern Analysis and Machine Intelligence, 11, (1989), 233--243.

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H. Li and M. Maresca, "Polymorphic-Torus Architecture for Computer Vision," IEEE Trans. Pattern Analysis and Machine Intelligence, vol. 11, no. 3, pp. 233-243, Mar. 1989.

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H. Li and M. Maresca, "Polymorphic-torus architecture for computer vision," IEEE Trans. on Pattern & Machine Intelligence , 11, 3, 133-143, 1989.

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H. Li and M. Maresca, "Polymorphic-torus architecture for computer vision," IEEE Trans. on Pattern & Machine Intelligence , 11, 3, 133-143, 1989.

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H. Li and M. Maresca, "Polymorphic-torus architecture for computer vision," 17 IEEE Trans. on Pattern & Machine Intelligence , 11, 3, 133-143, 1989.

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H. Li and M. Maresca, Polymorphic-torus architecture for computer vision, IEEE Trans. Pattern Analysis and Machine Intelligence, vol. 11, (1989) 233--243.

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