S. Hanono and S. Devadas. Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. In Proceedings of the 35th annual conference on Design Automation Conference, pages 510--515, San Francisco, California, United States, 1998. ACM Press.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....set of register files each connected to a dedicated set of functional units, e.g. Fig.2. Such an organization can significantly reduce the area delay power cost of storage and communication [4] but, if not properly accounted for during code generation, can result in degraded performance [5, 9, 10]. A number of researchers have suggested that the first phase in code generation for such clustered machines should be the binding of operations and variables to the datapath s clusters [5, 6, 11] In order to avoid penalties associated with data transfers, a key objective in performing cluster ....

.... [4] but, if not properly accounted for during code generation, can result in degraded performance [5, 9, 10] A number of researchers have suggested that the first phase in code generation for such clustered machines should be the binding of operations and variables to the datapath s clusters [5, 6, 11]. In order to avoid penalties associated with data transfers, a key objective in performing cluster assignment is to try to keep operations that share variables on the same cluster while still maximizing instruction level parallelism. However, since local storage resources have finite capacity ....

[Article contains additional citation context not shown here]

S. Hanono and S. Devadas. Instruction selection, resource allocation, and scheduling in the aviv retargetable code generator. In Proceedings of the 35th Design Automation Conference, 1998.

....optimizer is generated that is based on integer linear programming (ILP) It reads previously generated assembly programs and optimizes them. Experimental results show that large improvements can be achieved. In the past, research on retargetability has mainly focused on closed compilation systems [25, 26, 15, 14]. Using such a system in industry however mostly requires replacing the existing compiler infrastructure which causes high costs. Thus the use of retargetable compilers in industry is rare. Due to the postpass orientation, PROPAN can be integrated in existing tool chains with moderate effort and ....

....between them are addressed by graph based heuristic methods. The retargetable code generators MARION [4] CHESS [25] and CBC [8, 9] take phase interactions into account by heuristically estimating the effect of code generation decisions in one phase to other phases. The Express [14] and AVIV [15] compilers offer a heuristic coupling of code generation phases. In all these systems the quality of the generated code depends to a large degree on the quality of the chosen heuristics. The efficiency of a heuristics in turn depends on the specific target architecture so that a conflict between ....

S. Hanono and S. Devadas. Instruction Scheduling, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. In Proceedings of the Design Automation Conference

....generating optimal solutions for the given model. However, the complexity of the ILP solver allows computation of optimal solutions only for small benchmarks or only for some code generation subtasks. A heuristic phase coupled code generation technique (AVIV) for VLIW architectures is presented in [8]. Genetic algorithms have been proven very effective in finding optimal or near optimal solutions in huge search spaces. For this reason we are using a special list scheduling algorithm in combination with a genetic algorithm. In contrast to earlier work using genetic algorithms for scheduling ....

S. Hanonoand S. Devadas. Instruction Selection, Resource Allocation, and Scheduling in the Aviv Retargetable Code Generator. In Proceedings of the 35th DAC'98, 1998.

....scheme called CRAIG [4] that makes uses of information obtained from a pre pass scheduler for combining scheduling and register allocation phases. The compiler for TriMedia processor uses a technique much like the scheme in [2] to combine register allocation and scheduling [25] Hanono and Devadas [22], and Novak et al. [41] proposed code generation schemes for embedded processors, which combine the code selection, register allocation, and instruction scheduling phases. Motwani et al. provides NPcompleteness results of a simple instance of combined register allocation and instruction scheduling ....

S. Hanono and S. Devadas. Instruction selection, resource allocation, and scheduling in the Aviv retargetable code generator. In Proceedings of 35th Design Automation Conference, pages 510--515, 1998. 10

....nML has been used by the retargetable code generation environment CHESS [13] to describe DSP and ASIP processors. However, nML does not directly support multi cycle or multi word instructions. 3 ISDL also describes the processor in terms of its IS, with the goal of deriving a code generator ([9]) assembler and simulator. In ISDL, constraints on parallelism are explicitly specified through illegal operation groupings. This could be tedious for complex architectures like DSPs which permit operation parallelism (e.g. Motorola 56K) and VLIW machines with distributed register files (e.g. ....

S. Hanono and S. Devadas. Instruction selection,resource allocation,and scheduling in the AVIV retargetable code generator. In Proceedings of 35th Design Automation Conference, San Fransisco, CA, June 1998.

....nML has been used by the retargetable code generation environment CHESS [2] to describe DSP and ASIP processors. However, nML does not directly support multi cycle or multiword instructions. ISDL also describes the processor in terms of its IS, with the goal of deriving a code generator[12], assembler and simulator. In ISDL, constraints on parallelism are explicitly specified through illegal operation groupings. This could be tedious for complex architectures like DSPs which permit operation parallelism (e.g. Motorola 56K) and VLIW machines with distributed register files (e.g. TI ....

S. Hanono and S. Devadas. Instruction selection,resource allocation, and scheduling in the AVIV retargetable code generator. In Proc. DAC '98.

....between instructions are described implicitly by the grammar in a form of sets of legal combinations of operations. A good critique of nML is given in [15] ISDL is an ADL proposed at MIT [17] ISDL is mainly targeted towards VLIW processors. ISDL is used for automatic generation of compilers [18], assemblers, and cycle accurate simulators [19] Moreover, ISDL descriptions can be translated into synthesizable Verilog code. Similar to nML, ISDL mainly describes the instruction set of processors. The instruction set description includes action, assembly format, cost (reflecting execution ....

S. Hanono and S. Devadas. Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator. In Proc. of 35th DAC, 1998.

....(DFGs) has been presented [28] An improved approach, based on simulated annealing, has been described in [29] Mutation scheduling [30] is another approach to complete phase coupling, where also algebraic transformations are exploited in order to explore alternative instruction set mappings. In [31, 32], phase coupled compilers for certain classes of VLIW processors have been described. A constraint logic programming technique for DSPs with irregular architectures has been presented in [33] In that approach, all binding decisions are delayed until they are really required, which yields a ....

....is sufficient to explore different configurations of a given ASIP, thereby making hardware software trade offs. A significant amount of retargetable compiler technology for embedded processors is already available, including MSSQ [67] RECORD [68] SPAM [28] CHESS [69] CodeSyn [70] and AVIV [31]. Currently, retargetable compilers are receiving renewed interest also due to the need for architecture exploration at the system level: Retargetable compilers, in combination with simulators, can provide an early estimation of the performance of different target processors for a given ....

S. Hanono, S. Devadas: Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator, 35th Design Automation Conference (DAC), 1998

....set of register files each connected to a dedicated set of functional units, e.g. Fig.2. Such an organization can significantly reduce the area delay power cost of storage and communication [4] but, if not properly accounted for during code generation, can result in degraded performance [5, 9, 10]. A number of researchers have suggested that the first phase in code generation for such clustered machines should be the binding of operations and variables to the datapath s clusters [5, 6, 11] In order to avoid penalties associated with data transfers, a key objective in performing cluster ....

.... [4] but, if not properly accounted for during code generation, can result in degraded performance [5, 9, 10] A number of researchers have suggested that the first phase in code generation for such clustered machines should be the binding of operations and variables to the datapath s clusters [5, 6, 11]. In order to avoid penalties associated with data transfers, a key objective in performing cluster assignment is to try to keep operations that share variables on the same cluster while still maximizing instruction level parallelism. However, since local storage resources have finite capacity ....

[Article contains additional citation context not shown here]

S. Hanono and S. Devadas. Instruction selection, resource allocation, and scheduling in the aviv retargetable code generator. In Proceedings of the 35th Design Automation Conference, 1998.

....methods that allow to calculate exact, optimal solutions usually at the cost of higher calculation times. Since in digital signal or realtime applications code quality is extremely important, higher calculation times are acceptable within reasonable limits. The AVIV retargetable code generator [13] builds on the SPAM library which is a retargetable code generation framework for digital 2 signal processors [28] AVIV uses a branch andbound algorithm that performs functional unit assignment, operation grouping, register bank allocation, and scheduling. Detailed register allocation is carried ....

S. Hanono and S. Devadas. Instruction Scheduling, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. In Proceedings of the DAC. ACM, 1998.

....for each instruction. The pipeline structure is not explicitly described. Constraints on ILP posed by conflicts 1 , are explicitly described in a form of a set of Boolean rules all of which must be satisfied for an instruction to be valid. ISDL is used for automatic generation of a compiler [16], an assembler, and a cycle accurate simulator [14] ISDL descriptions can also be translated into synthesizable Verilog code. Valen C is an embedded software programming language proposed at Kyushu University [19, 20] ValenC is an extended C language which supports explicit and exact bit width ....

....to retarget their transformations (e.g. instruction selection requires a description of the semantics of each operation) Explicit behavioral information based retargetable compilers require full information about the IS as well as explicit resource conflict information. Examples include the AVIV [16] compiler using ISDL, CHESS [22] using nML, and Elcor [40] using MDes. The AVIV retargetable code generator produces machine code, optimized for minimal size, for target processors with different IS. It solves the phase ordering problem by performing a heuristic branch and bound step that performs ....

S. Hanono and S. Devadas. Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator. In Proc. of 35th Design Automation Conf., pages 510--515, 1998.

....that all CSEs are stored to memory and all but one CSE uses are loaded from memory, which is not always necessary. The same limitation holds for the binate covering formulation given in [7] which presents an exact technique for mapping DFGs to DSP data paths. A further approach is presented in [8], which uses a branch and bound algorithm for DFG code generation. However, unlike [6] and [7] it separates detailed register allocation from code selection. Thus, for architectures with single special purpose registers (instead of register les) like the one shown in g. 1, it may generate ....

S. Hanono, S. Devadas: Instruction Selection, Resource Allocation, and Scheduling in the AVIV retargetable code generator, 35th Design Automation Conference (DAC), 1998

....University and MIT. Although SPAM can be classified as a retargetable compiler, it is more based on exchangeable software modules performing specific optimization instead of an external target processor model. Another approach to retargetable code generation for PDSPs is the AVIV compiler [90], which uses a special language (ISDL [91] for modeling VLIW like processor architectures. As compilers for standard DSPs and ASSPs become more important and retargetable compiler technology gets more mature, several companies have started to sell commercial retargetable compilers with special ....

S. Hanono, S. Devadas. Instruction Selection, Resource Allocation, and Scheduling in the AVIV retargetable code generator. 35th Design Automation Conference (DAC), 1998.

....nML has been used by the retargetable code generation environment CHESS [1] to describe DSP and ASIP processors. However, nML does not directly support multi cycle or multi word instructions. ISDL also describes the processor in terms of its IS, with the goal of deriving a code generator ([12]) assembler and simulator. In ISDL, constraints on parallelism are explicitly specified through illegal operation groupings. This could be tedious for complex architectures like DSPs which permit operation parallelism (e.g. Motorola 56K) and VLIW machines with distributed register files (e.g. TI ....

S. Hanono and S. Devadas. Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator. In Proc. DAC, 1998.

....Very Long Instruction Word (VLIW) architectures. In this paper we focus on the methodology which allows us to generate two of the tools from ISDL: the ILS and the hardware implementation model (corresponding to the shaded boxes in Figure 1) The design of the retargetable compiler is covered in [2]. The design of the assembler generator is briefly described in [3] 1.1 Organization of this paper Section 2 presents a brief overview of the ISDL machine description language, with emphasis on the features that make simulator generation and hardware synthesis possible. Section 3 presents the ....

S. Hanono and S. Devadas. Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. In Proceedings of the 35 th Design Automation Conference, pages 510-- 515, 1998.

....code generator a code generator that can automatically generate code for different target architectures is required. This thesis focuses on the task of retargetable code generation. The major contribution of this thesis is the presentation of the Aviv retargetable code generator [26] which automatically produces optimized machine code for a variety of target processor architectures. In addition, this thesis presents the Instruction Set Description Language (ISDL) 23, 22] which is a machine description language that was developed to support the communication between the ASIP ....

S. Hanono and S. Devadas. Instruction selection, resource allocation, and scheduling in the Aviv retargetable code generator. In Proceedings of the 35th Design Automation Conference, pages 510--515, June 1998. 227

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S. Hanono and S. Devadas. Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. In Proceedings of the 35th annual conference on Design Automation Conference, pages 510--515, San Francisco, California, United States, 1998. ACM Press.

No context found.

S. Hanono, S. Devadas: Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator, 35th Design Automation Conference (DAC), 1998

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S. Hanono, S. Devadas: Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator, 35th Design Automation Conference (DAC), 1998

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S. Hanono and S. Devadas. Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator. In Proc. DAC, 1998.

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S. Hanono and S. Devadas. Instruction Scheduling, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. In Proceedings of the Design Automation Conference 1998, San Francisco, California, 1998. ACM.

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S. Hanono, S. Devadas. Instruction Selection, Resource Allocation, and Scheduling in the AVIV retargetable code generator. 35th Design Automation Conference (DAC), 1998. 49

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S. Hanono and S. Devadas. Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. In 35th Design Automation Conference, pages 510--515, 1998.

No context found.

S. Hanono and S. Devadas. Instruction Scheduling, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. In Proceedings of the Design Automation Conference 1998, San Francisco, California, 1998. ACM.

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Silvia Hanono and Srinivas Devadas. Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. In in Proc. of 35th Design Automation Conference(DAC), June 1998.

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