R. Ubar, "Test Synthesis with Alternative Graphs", IEEE Design & Test of Comp., Spring 1996. Home/Search Document Not in Database Summary Related Articles Check |
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Genetic Algorithms in Test Pattern Generation - Ivask (1998) (Correct)
....part and a memory part (a set of flip flops) 2) in the functional way by STDs. The output functions and transition functions of the FSM are Boolean, and therefore can be represented by Structurally Synthesized BDDs (SSBDD) 16] For the second case, we use a general form of decision diagrams [17] which exploit integer variables for representing inputs, outputs and internal states of the FSM. In these graphs, node variables may have, in general, more than two values. There exists a one to one correspondence between the values of a node variable and the successors of the node. The number of ....
R.Ubar, Test Synthesis with Alternative Graphs. IEEE Design&Test of Computers, Spring 1996, pp. 48-57.
Hierarchical Test Generation Based on Alternative Graph Models - Raik (1997) (Correct)
....test, functional test generation does not guarantee a very good correspondence with real physical defects. Current thesis presents a hierarchical test generation approach working on architectural (register transfer) and gate levels. The approach uses multi level alternative graph (AG) Ubar 76, Ubar 96a] descriptions for design modelling. The main advantage of AG models lies in the fact that a uniform concept can be applied on different system abstraction levels. In addition, alternative graph models provide a powerful means for solving different diagnostic tasks. 5 3 Alternative Graphs 3.1 ....
....models lies in the fact that a uniform concept can be applied on different system abstraction levels. In addition, alternative graph models provide a powerful means for solving different diagnostic tasks. 5 3 Alternative Graphs 3. 1 Basic Definitions Definition: Alternative Graph (AG) Ubar 76, Ubar 96a] can be defined as a directed non cyclic labelled graph in the form of a quadruple G= V,A,Z,D) where V is a finite set of vertices (referred to as nodes) A is a finite set of arcs (branches) Z is a function which defines the variables labelling the nodes and the variable domains, and D is a ....
R.Ubar, "Test Synthesis with Alternative Graphs", IEEE Design and Test of Computers, Vol.13, No. 1, pp. 48-57, Spring 1996.
A Hierarchical Test Generation Technique for Embedded Systems - Jervan, Eles, Peng (1999) (Correct)
....analysis for this particular problem has been studied, but not many efficient techniques have been developed yet. In our approach, testability evaluation and test generation at the system level are based on hierarchical test generation (HTG) 9] We apply HTG, using a decision diagram (DD) [12] based representation, and show that it can be used for both the hardware and software domains as well as for different levels of abstraction. 2. Hierarchical Test Generation for Hardware Software Systems Test generation has been proven to be an NP complete problem [6] There has been a lot of ....
....be Implemented in Software In our approach, decision diagrams are used for design modeling at the high abstraction levels. The main advantage of modelling with DDs lies in the fact that a uniform concept can be applied on different abstraction levels. An extended overview of DDs is presented in [12]. Our main objectives are to show how DDs can be used for test generation at the behavioural level and how HTG can be used for testing the part of the system which finally will be implemented as software. Hierarchical test generation technique for hardware has been reported at [8] At this level, ....
R. Ubar, "Test Synthesis with Alternative Graphs," IEEE Design and Test of Computers, Vol. 13, No. 1, pp. 48-57, Spring 1996
High-Level Test Synthesis with Hierarchical Test Generation - Gert Jervan Petru (1999) Self-citation (Ubar) (Correct)
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R. Ubar, "Test Synthesis with Alternative Graphs", IEEE Design & Test of Comp., Spring 1996.
Hierarchical Test Generation with Multi-Level Decision.. - Jervan, Markus, Raik.. (1998) Self-citation (Ubar) (Correct)
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R. Ubar, "Test Synthesis with Alternative Graphs", IEEE Design & Test of Computers, pp. 4857, Spring 1996.
DECIDER: A Decision Diagram Based Hierarchical Test.. - Gert Jervan Antti (1998) Self-citation (Ubar) (Correct)
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R. Ubar. Test Synthesis with Alternative Graphs. IEEE Design & Test of Computers, pp. 48-57, Spring 1996.
Unknown - Proc Rd International Self-citation (Ubar) (Correct)
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R. Ubar, "Test Synthesis with Alternative Graphs," IEEE Design & Test of Computers. Spring 1996, pp. 48-59.
High-Level Test Synthesis from Behavioral Descriptions - Gert Jervan Petru Self-citation (Ubar) (Correct)
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R. Ubar, "Test Synthesis with Alternative Graphs", IEEE Design & Test of Comp., Spring 1996.
Turbo Tester: A Cad System For Teaching Digital Test - Jervan Markus Paomets (1998) Self-citation (Ubar) (Correct)
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R. Ubar, "Test Synthesis with Alternative Graphs", IEEE Design and Test of Computers, Vol.13, No. 1, pp. 48-57, Spring 1996.
JOURNAL OF ELECTRONIC TESTING: Theory and Applications.. - Springer Science.. Self-citation (Ubar) (Correct)
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R. Ubar, "Test Synthesis with Alternative Graphs," IEEE Design &Test of Computers, Spring 1996, pp. 48--57.
DECIDER: A Decision Diagram Based Hierarchical Test.. - Gert Jervan Antti (1998) Self-citation (Ubar) (Correct)
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R. Ubar. Test Synthesis with Alternative Graphs. IEEE Design & Test of Computers, pp. 48-57, Spring 1996.
Cad Software for Digital Test and Diagnostics - Jervan, Markus, Paomets, Raik, .. Self-citation (Ubar) (Correct)
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R.Ubar, Test Synthesis with Alternative Graphs. Design & Test of Computers, Spring 1996, pp. 48-57.
SSBDDs: Advantageous Model and Efficient Algorithms - For Digital Circuits Self-citation (Ubar) (Correct)
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R. Ubar, "Test Synthesis with Alternative Graphs," IEEE Design & Test of Computers. Spring 1996, pp. 48-59.
High-Level Path Activation Technique to Speed Up Sequential.. - Raik, Ubar Self-citation (Ubar) (Correct)
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R. Ubar, "Test Synthesis with Alternative Graphs", IEEE Design & Test of Computers, pp. 48-57, Spring 1996.
Cycle-based Simulation with Decision Diagrams - Raimund Ubar Adam (1999) Self-citation (Ubar) (Correct)
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R.Ubar. "Test Synthesis with Alternative Graphs.", IEEE DesignTest of Comput., Spring 1996, pp.48-57
Testability Guided Hierarchical Test Generation with.. - Raimund Ubar Jaan Self-citation (Ubar) (Correct)
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Ubar R. Test Synthesis with alternative graphs. IEEE Design & Test of Computers. Spring 1996, pp.48-57.
High-Level Path Activation Technique to Speed Up Sequential.. - Jaan Raik Raimund Self-citation (Ubar) (Correct)
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R. Ubar, "Test Synthesis with Alternative Graphs", IEEE Design &Test of Computers, pp. 48-57, Spring 1996.
Sequential Circuit Test Generation Using Decision Diagram Models - Jaan Raik Raimund (1999) Self-citation (Ubar) (Correct)
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R. Ubar, "Test Synthesis with Alternative Graphs", IEEE Design & Test of Computers, pp. 48-57, Spring 1996.
Fast Test Pattern Generation for Sequential Circuits Using.. - Raik, Ubar (2000) (1 citation) Self-citation (Ubar) (Correct)
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R. Ubar, "Test Synthesis with Alternative Graphs," IEEE Design & Test of Computers, pp. 48--57, Spring 1996.
A Decision Diagram based Hierarchical Test Pattern Generator - Jervan Markus Raik Self-citation (Ubar) (Correct)
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R. Ubar, "Test Synthesis with Alternative Graphs", IEEE Design & Test of Computers, pp. 48-57, Spring 1996.
Timing Simulation of Digital Circuits with Binary Decision.. - Ubar, Jutman, Peng (2001) Self-citation (Ubar) (Correct)
....gate delays. A novel method for delay simulation is developed based on Boolean derivatives and structurally synthesized binary decision diagrams (SSBDD) SSBDDs were introduced the first time in [3,4] as structural alternative graphs, and generalized for the multiple valued decision diagrams in [5]. In [6] SSBDDs were suggested for multivalued simulation of digital circuits for different purposes like hazards investigation [7] delay fault analysis [8] and fault cover analysis in dynamic testing [9] When using SSBDDs for representing macros, the complexity of the model will be ....
....a transition pattern given in Table 2. The bold arrows (in Fig. 2) mark the activated path in the graph before the transition. The shaded nodes are those involved in the transition, i.e. where the direction of the activated path changes. For the nodes g and h 1 we have max y g = max y h 1 = 1 [5]. Using the formula (2) we find that g h 1 = h e = U which means that at time t = 3 we may have a glitch on the output of the circuit. 5. The Timing Simulation Algorithms Using the SSBDD model gives us the possibility to minimize the number of macro inputs to be processed as well as the ....
R. Ubar. Test Synthesis with Alternative Graphs. IEEE Design & Test of Computers. Spring 1996, pp. 48-59.
Cycle-Based Simulation Algorithms for Digital Systems Using.. - Raimund Ubar Jaan (2000) Self-citation (Ubar) (Correct)
....HDL based simulation approach [1] The general objective of the presented work is to improve the simulation performance of the DD based system representation by introducing the event driven paradigm to the cycle based simulation of the network of DDs. 2. Algorithms DDs have been described in [1,2] as a representation of digital systems given at various levels of abstraction. DDs are used in the paper to increase the speed of local simulation of components or subcircuits of the system. Three simulation algorithms are introduced to implement the idea of simulation execution according to ....
R.Ubar, "Test Synthesis with Alternative Graphs.", IEEE Design&Test of Computers, pp 48-57, Spring 1996.
Exploiting High-Level Descriptions for Circuits Fault.. - Benso Prinetto.. Self-citation (Ubar) (Correct)
....the lower level. 1. The model In our approach, Alternative Graphs are used for high level modeling of digital systems and fault simulation. AGs were introduced for representing the functions of a system in the form of decision diagrams to reveal explicitly the signal cause effect relationships [9]. Fig.1. VHDL example of a digital system By tracing an AG model of a system for a given time moment (status) and input pattern, we determine a subset of nodes (variables) which are responsible for the system s behavior at this moment. If the system has a failure, then only the mentioned subset ....
R. Ubar, Test Synthesis with Alternative Graphs, IEEE Design & Test of Comp., 1996 Spring, pp. 4857.
A New Approach to Build a Low-Level Malicious.. - Benso, Prinetto.. (1997) Self-citation (Ubar) (Correct)
....on the fault tree is employed. The method proposed is very costly in terms of CPU time and it seems not applicable to more complex systems. In this paper a new approach to generate a malicious fault list is presented, based on two different levels: at a high level, alternative graphs (AGs) [9,11] are applied to build the fault tree; a fault collapsing is then made on that tree, and the reduced fault list is converted so that it can be used together with the low level description. The approach developed in this paper helps to overcome the complexity problem inherent in low level ....
....of the system; create a High level Fault List; generate a High level Malicious Fault List and collapse the High level Fault List using AG simulation; translate the obtained High level Fault List into a Low level Fault List. 3. Alternative graphs and digital systems Alternative Graphs [9,11] can be used for representing digital functions y = F(Z) of components or subcircuits in digital systems. Here, y is an output variable and Z is a vector of input variables of a component. Alternative Graph is a directed acyclic graph G y = M, G, Z) with a set of nodes M, with a single root node ....
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R. Ubar, Test Synthesis with Alternative Graphs, IEEE Design & Test of Computers, 1996 Spring, pp. 48-57.
TIMA Research Report May 1998 1 - Generation Of Self-citation (Ubar) (Correct)
....from [1] where only the diagnosis problem is formulated and solved, in the present paper, the error detection and error diagnosis tasks are solved jointly which allows to increase the efficiency of error localization. The originality of this paper lies in using structurally synthesized BDDs [7, 8] which allowed to develop efficient higher level path activation and fault reasoning procedures for increasing the speed in test generation and fault diagnosis. The method is based on the stuck at fault model, where all the analysis and reasoning is carried out in terms of stuck at faults and only ....
....1 NOT(x 1 ) 0 1 NOT(x 2 ) 0 1 NOT(x 2 ) Table 1: Mapping between stuck at faults and gate errors 4. Representing circuits by macros and SSBDDs We now consider a method which was developed for macro level test generation based on using structurally synthesized BDDs (SSBDD) as the model for macros [7]. Test patterns are generated at the macro level, however the fault (and error) diagnosis is made at the gate level. Therefore, a correspondence should be established to map the macro level results back to the gate level. Consider a given implementation as a network of macros NF = f k , where ....
[Article contains additional citation context not shown here]
R. Ubar. Test Synthesis with Alternative Graphs (R.Ubar). IEEE Design and Test of Computers. Spring, 1996, pp.48-59.
Report on Early DfT Support - ELES, JERVAN, MOHAMMED, PENG (2000) (1 citation) (Correct)
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R. Ubar, "Test Synthesis with Alternative Graphs", IEEE Design and Test of Computers, Vol. 13, No. 1, pp. 48-57, Spring 1996.
High-Level Test Generation and Built-In . . . - Jervan (2002) (Correct)
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R. Ubar, "Test Synthesis with Alternative Graphs," IEEE Design and Test of Computers, Vol. 13, No. 1, pp. 48-57, Spring 1996.
High-Level and Hierarchical Test Sequence Generation - Jervan, Peng, Goloubeva.. (2002) (Correct)
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Ubar R., "Test Synthesis with Alternative Graphs," IEEE Design and Test of Computers, Vol. 13, No. 1, 1996, pp. 48-57.
Specification - System Synthesis Hardware (Correct)
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R. Ubar, "Test Synthesis with Alternative Graphs," IEEE Design and Test of Computers, Vol. 13, No. 1, pp. 48-57, Spring 1996
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