R. F. Lyon, "Two's complement pipeline multipliers," IEEE Transactions on Communications, vol. 12, pp. 418--425, April 1976.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....of t independently is desirable, allowing all the inputs, outputs and intermediate variables of the operator to be 16 bit long. Using this scheme and duplicating hardware, the throughput of a modular multiplication operation can be doubled. A modified version of Lyon s parallel serial multiplier [26] was developed which addresses this problem. To generate two 16 bit results in 16 cycles, the throughput of the multiplier must be doubled. We achieved this by duplicating the hardware for multiplication, as illustrated in Figure 3. Registers storing the constant are shared among the two ....

R. F. Lyon, "Two's complement pipeline multipliers," IEEE Transactions on Communications, vol. 12, pp. 418--425, April 1976.

....interpreted as registers. Finally the last equation shows that the b th bit of the result is output by the last (W 1 th) processor at time b 2W 1. The complete program describes a virtual linear array (Fig.2) composed of elementary cells similar to the first W Gamma 1 cells of Lyon s multiplier [10]. Additional program transformations will lead to a program which may be interpreted as low level hardware, expressed in a subset of Alpha called AlpHard[8] which has the following characteristics: ffl hierarchical structuring (because design process is itself hierarchical) ffl genericity (to ....

R. F. Lyon. Two's complement pipeline multipliers. IEEE Trans. Comm., 24:418--425, April 1976.

....else A; 6c t = 1: if C then B else B; 6d esac; c) Actual AlpHard description Figure 2: Multiplexers and feedback in AlpHard. 3 Lyon s bit serial multiplier We now present the AlpHard specification of a well known two s complement bit serial multiplier, originally due to Lyon [Lyo76]. It is a classic sytolic array, although it even predates the work of Kung and Leiserson [KL80] who first introduced the phrase systolic arrays. It is implemented as a linear network of elementary boolean cells, as shown in figure 3. 3.1 Algorithmic Description of the Multiplier Consider two ....

R. F. Lyon. Two's complement pipeline multipliers. IEEE Trans. Comm., COM24: 418--425, April 1976.

....domain of the restriction (i.e. the constraints before the colon) corresponds to the indices where the control signal is either true or false. 3 Lyon s bit serial multiplier We now present the AlpHard specification of a well known two s complement bit serial multiplier, originally due to Lyon [Lyo76]. It is a classic sytolic array, although it even Irisa Generating Regular Arithmetic Circuits with AlpHard 7 B C A S 0 1 (a) A simple circuit (b) Naive AlpHard description 1 system MuxEx (A,C: t 0 =t of boolean) 2 returns (S: t 0 =t of boolean) 3 var B: t 1 =tof boolean; 4 let ....

R. F. Lyon. Two's complement pipeline multipliers. IEEE Trans. Comm., COM24: 418--425, April 1976.

.... in the C 6 block is described in detail in [21] The adder and multiplier circuit structures are crucial since they contribute the largest portion of delay in the critical path formula shown in (9) Thus, a parallel and modular structure should be proposed similar to the ones introduced in [22] [23]. Furthermore, several other designs can be applied [24] 25] 26] 27] 28] 29] in order to further exploit the advantages of CMOS VLSI technology. A recently introduced design style used to improve the performance of VLSI circuits is the Wave Pipelining technique [30] 31] Several design ....

R.F. Lyon. Two's Complement Pipeline Multiplier. IEEE Transactions on Communications, 24:418--425, April 1976.

....t independently is desirable, allowing all the inputs, outputs and intermediate variables of the operator to be 16 bit long. Using this scheme and duplicating hardware, the throughput of a modular multiplication operation can be doubled. A modified version of Lyon s serial parallel multiplier [20] was developed which addresses this problem. The original design of Lyon s multiplier is shown in Figure 4. To generate two 16 bit results in 16 cycles, the throughput of the multiplier must be doubled. We achieved this by duplicating the hardware for multiplication, as illustrated in Figure 5. ....

R. F. Lyon, "Two's complement pipeline multipliers, " IEEE Transactions on Communications, vol. 12, pp. 418--425, April 1976.

....thus describes a virtual linear array (Fig.2a) This design is still very abstract. Additional lower level program transformations are needed to turn control information present in the domains into systolic control variables [13] In our example we get a bit serial multiplier similar to Lyon s [10]. The resulting Alpha program may then be translated [8] into structural VHDL for synthesis by commercial VLSI CAD tools like Compass or Synopsys. We will come back to these transformations in section 3.4. Program 3 Fixed point bit serial multiplier 1 system times . 2 var 3 ....

R. F. Lyon. Two's complement pipeline multipliers. IEEE Trans. Comm., 24:418-425, April 1976.

....These control signals localized to each data bits are called the head bits. For the timing of the control signal relative to the data signal, most bit serial multiplier designers have used the timing where the control signal becomes active at the same time as the LSB is present at the data wire [68][11] A different timing is used where the control signal becomes active 1 clock cycle before the LSB arrives (Fig.3.1) 3.1.3 Operation Latency Operation latency is often measured from the arrival time of the first bit of the input to the time the first bit of the output is produced. Here, the ....

....described as Y = 2 k 1 X is implemented by the circuit described in Fig.3.9(d) The figure describes the circuit for double precision variables with overflow extension. The latency ffi is 1. 3.2. 4 Multiplication Bit serial multiplication have been investigated by many researchers until now [68][73] 11] 52] The criteria of the quality of the bit serial multiplication schemes are 1. Ability to handle 2 s complement number. 2. Ability to produce double precision product. 3. Operation clock frequency. 4. Throughput. 5. Latency. 6. Circuit complexity. Among them, Algorithm proposed ....

[Article contains additional citation context not shown here]

R. E. Lyon, "Two's Complement Pipeline Multipliers," IEEE Trans. Computers, pp.418-425, 1976.

.... and massively parallel with simple processing elements (PEs) The idea of using such regular circuits was even present in von Neuman s cellular automata in the fifties, Hennie s iterative logic arrays in the sixties, and also in specialized arithmetic circuits (Lyon s bit serial multiplier [1] is clearly a linear systolic array) However, the emergence of vlsi technology in the late seventies and early eighties made the time ripe for introducing such architectures in order to highlight the characteristics appropriate to the technology. Systolic arrays immediately caught on, since they ....

Lyon, R.F., "Two's complement pipeline multipliers," IEEE Transactions on 32 Emerging Technologies Computers, vol. COM-24, pp. 418--425, April 1976.

....while the other is entered serially. However, this scheme is not always possible, as, for instance, when both factors are input serially at the same time. In such cases a multiplier with two serial inputs is needed. An example of serial input and output multiplier was presented by R. F. Lyon [1]. Its salient feature is a high throughput obtained at the expenses of a truncated output. Fullprecision modular serial multipliers for unsigned numbers were introduced by H. J. Sips [2] and by N. R. Strader and V. T. Rhyne [3] In a similar paper, R. Gnanasekaran [4] presented the first ....

R. F. Lyon. Two's complement pipeline multipliers. IEEE Transactions on Communications, COM-24(4):418--25, April 1976.

....for comparison. In addition, the performance of the FPGA based multipliers will be compared to that of custom multiplication chips. 3. 1 Multiplication architectures When choosing an architecture for a hardware digital multiplier two basic alternatives are available: parallel and bit serial [22] [29] [25] In between these two choices there exists a full range of combinations of parallel and serial architectures [30] that can be considered neither fully parallel nor fully serial but rather are a combination of the two techniques such as with a nibble serial multiplier. Only the two extremes ....

....in the table The architectures used for the multipliers implemented on the FPGAs were common parallel multiplier arrays such as the Baugh Wooley two s complement array multiplier [22] 25] and straightforward implementations of pipelined versions of the bit serial multiplier shown in Figure 3. 2 [29]. In addition, a few versions of parallel multipliers that take advantage of the special logic features available on the Altera and Xilinx FPGAs were created. These are intended to represent near the absolute maximum possible multiplier performance that can be achieved with these current FPGAs. In ....

R.F. Lyon. Two's complement pipeline multipliers. IEEE Transactions On Communications, pages 418--424, April 1976.

....Slice 32 2 2 2 2 Host Addr. A p s reg. B p s reg. S p s reg. Cntr. Figure 5: Long multiplication PAMs may be configured as long integer multipliers [SBV91] They compute the product P = A Theta B S where A is an n bit long multiplier, and B; S are arbitrary size multiplicands and summands [Lyo76]; n may be up to 2k for the P 1 implementation. Our multipliers are interfaced with the arbitrary precision arithmetic package BigNum [SVH89] programs based on that software automatically benefit from the PAM, by simply linking with a modified BigNum library. P 1 computes product bits at 66 ....

R. F. Lyon, Two's complement pipeline multipliers, IEEE Transactions on Comm., COM-24:418-425, 1976.

....x Mult. Slice 32 2 2 2 2 Host Addr. A p s reg. B p s reg. S p s reg. Cntr. Fig. 7. Long multiplication PAMs may be configured as long integer multipliers [18] They compute the product P = A Theta B S where A is an n bit long multiplier, and B; S are arbitrary size multiplicands and summands [19]; n may be up to 2k for the P 1 implementation. Our multipliers are interfaced with the public domain arbitrary precision arithmetic package BigNum [20] programs based on that software automatically benefit from the PAM, by simply linking with an appropriatedly modified BigNum library. P 1 ....

R. F. Lyon, "Two's complement pipeline multipliers", IEEE Trans. on Comm., vol. COM-24, pp. 418--425, 1976.

.... A majority of bit level systolic designs are two dimensional structures (e.g. multibit convolver, correlator, rank order filter [MCMW87] divider [MQMC92, DaFe92] and square rooter [MQMC92] while a few are one dimensional (linear) arrays (e.g. radix 2 and radix 4 digit slice multipliers [Lyon76, MCMW86, IrOw89], adder [IrOw87] and FIR filter [IrOw89] Linear configurations offer a reduced amount of hardware and simpler construction over two dimensional designs [Foun88] However, some arithmetic operations such as division and square root have been difficult to implement in a bit level linear array ....

R.F. Lyon, "Two's Complement Pipeline Multipliers," IEEE Trans. on Communications, Vol COM-24, No. 4, April 1976, pp. 418-425.

....Ps pReg 32 32 2 2 2 2 512 2K x Mul. Slice Mul. Cntr Host Adr. Host Data A Reg We have programmed both PAMs into long multipliers (n = 512 bits for P 0 , and n = 2K bits for P 1 ) computing P = A Theta B S, with A a n bit multiplier, and B; S arbitrary size multiplicands and summands (see [Lyo76], BRV89] and [SBV91] These multipliers are interfaced with an arbitrary precision arithmetic package BigNum (see [SVH89] so that any program based on that software takes advantage of the PAM without modification, by simply relinking with a modified BigNum library. This respectively speeds up ....

R.F. Lyon. Two's complement pipeline multipliers. IEEE Trans. Comm., 24:418-- 425, 1976.

....Ps pReg 32 32 2 2 2 2 512 2K x Mul. Slice Mul. Cntr Host Adr. Host Data A Reg We have programmed both PAMs into long multipliers (n = 512 bits for P 0 , and n = 2K bits for P 1 ) computing P = A Theta B S, with A a n bits multiplier, and B; S arbitrary size multiplicands and summands (see [Lyo76], BRV89] and [SBV91] These multipliers are interfaced with an arbitrary precision arithmetic package BigNum (see [SVH89] so that any program based on that software takes advantage of the PAM without modification, by simply relinking with a modified BigNum library. This respectively speeds up ....

R.F. Lyon. Two's complement pipeline multipliers. IEEE Trans. Comm., 24:418--425, 1976.

....is built from a certain number of butter y elements. Each of these elements is made primarily of a complex multiplier and two adders. A complex multiplier is made of four real multipliers and two adders. A bit serial Lyon xed point multiplier is a systolic array made of two types of basic cells [6] 1 . Finally each cell is made of a few gates and registers. The lowest level The base bricks of a design are primitive gates and simple base blocks, either combinatorial (a full adder. or sequential (a small nite state machine, the basic cell the bit serial multiplier on Fig. 1. The ....

R. F. Lyon. Two's complement pipeline multipliers. IEEE Trans. Comm., 24:418-425, April 1976.

No context found.

R. F. Lyon, "Two's complement pipeline multipliers," IEEE Trans. Commun. 24, 418--425 119762.

No context found.

R. F. Lyon. Two's complement pipeline multipliers. IEEE Trans. Comm.,24:418-- 425, 1976.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC