H. Trickey. "Flamel: A high level hardware compiler". In IEEE Trans. on CAD, pages 259--269, Mar 1987.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....the behavioral description of a system into structural or architectural representation. The Yorktown Silicon Compiler [62] MacPitts [66] and Silc [84] are among the early synthesis systems that were proposed. These systems were followed by others with more comprehensive set of algorithms. [64] proposes a hardware compiler called Flamel that takes programs written in Pascal and generates optimized hardware by identifying parallelism in them. Haroun and Elmasry in [50] present SPAID: A novel design methodology for DSP algorithm synthesis. Various transformations in SPAID include ....

H. Trickey. "Flamel: A high level hardware compiler". In IEEE Trans. on CAD, pages 259--269, Mar 1987.

.... distributivity and commutativity are the three most often used algebraic transformations [Wae50] Most often they are treated under the paradigm of tree height reduction, although several authors discuss in detail the critical path minimization of general DAG s (directed acyclic graph) [Tri87, Har89, Lob91, Dun92]. Recently, algebraic transformations have been generalized to cover other algebraic axioms such as inverse elements (e.g. and were applied with the goal of minimizing design area under throughput and latency constraints [Pot91] Other algebraic transformations are related to other axioms in ....

H. Trickey: "Flamel: A High-Level Hardware Compiler", IEEE Transaction on CAD, Vol. 6, No. 2, pp. 259269, 1987.

....but of lower gate capacity. 4 AT T s (Lucent) ORCA series is another well known LUT based (SRAM) family of stand alone FPGAs. 3 approach have been developed: 1. Data ow graphs as in Sehwa [17] MAHA [18] HAL [19] and the Pangrle system [4] 2. High level languages, for example Pascal [20], Ada [21] 3. Enhanced versions of existing languages such as HandelC, HardwareC [22] or HardwarePal [23] 4. Hardware description languages such as ISPS [24] CADDY DSL [25] Verilog [26] or VHDL [27] Data ow diagrams may well be suitable for hardware independent, conceptual descriptions of ....

H. Trickey. Flamel: A high-level hardware compiler. IEEE Transactions on Computer-Aided Design, 6(3):259-269, 1987.

....today s FPGAs, with lower gate counts and slower speeds. The need to exploit fine grain parallelism is important because of frequently encountered small sized critical sections. A substantial amount of work in hardware synthesis has been reported in the literature. These efforts include Flamel [13] a Pascal to hardware compiler, IBM s HIS system [14] which translates a VHDL behavioral description into a synchronous digital machine, and Cyber [15] which compiles programs in C and BDL into ASIC chips. In addition, Camposano [16] and Walker [17] report a survey of different highlevel ....

....successfully addresses the issue of execution of loops with dynamic loop counts, and executes control constructs such as if then else and switch case , efficiently. Second, the model possesses some key advantages over existing models proposed in traditional high level synthesis architectures [13], 14] and [15] Traditional highlevel synthesis architectures utilize centralized controllers that fail to exploit potential fine grain parallelism. In contrast, such restrictions are absent in PRISM II. In addition, unlike in the above architectures, the PRISM II execution model permits direct ....

Howard Trickey. Flamel: A high-level hardware compiler. IEEE Transactions on Computer-Aided Design, CAD-6(2), March 1987.

....was sponsored by the ESPRIT2260 ( SPRITE ) project of the EC. Transformations are often used for optimisation purposes. In parallel compilers, transformations are used to exploit parallelism in flow graphs [1, 2] In high level synthesis, transformations are mainly used to optimise throughput [3, 4, 5]. Recently, transformations are also used in power optimisation [6] where the steering is limited to a generic global optimisation technique on a subset of the possible transformations. Also using transformations for direct area optimisation has not yet attracted much attention. Local resource ....

H. Trickey, "Flamel: A high-Level Hardware Compiler, " IEEE Transactions on CAD, Vol. 6, No. 2, pp. 259-269, 1987.

....transformations,unlikecompiler relatedoptimizationtechniques forwhichspeedistheprimaryobjective. Inhigh levelsynthesis,transformationsforthroughputand poweroptimizationfordata flowintensive(DFI)behavioraldescriptions [5] 6] aswellascontrol flowintensive(CFI)behaviors [7], 8]havebeenpresented.NoneofthesetransformationtechniquesforCFIbehaviorstargetspoweroptimization. Withtheexceptionof [8] thesesystemsdonotincorporateschedulinginformationintothetransformationapplicationprocess. ....

....Results The techniques described in this paper were implemented in a program called FACT , written in C . We evaluated this program by using it to transform several commonly available benchmarks, to optimize for throughput and power. We compare our method, FACT , with the technique presented in [7] (Flamel) and another technique, which will be called M1 for the remainder of this discussion. Flamel applies the same transformation suite as our method does, and also has the ability to transcend basic blocks in its optimization, which makes it an ideal candidate for comparison. All Table 2: ....

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H. Trickey, "Flamel: A high-level hardware compiler," IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 259--269, Mar. 1987.

....is to further optimize the (relatively small) common case behavior aggressively using known power and performance optimization techniques. Since the common case operations extracted from the schedule are represented at the behavior level, a natural choice is to use behavioral transformations [9, 10, 13, 14] to simplify them. We use a powerful transformation framework to apply various transformations aimed at minimizing the number of operations, and the critical path, of the common case behavior. For the GCD example, the initial common case behavior shown in Figure 2(a) is automatically transformed ....

....execution circuit. In this step, optimizing transformations are applied to simplify the common case behavior, prior to synthesis. Power optimizing transformations have been extensively studied in the literature [10, 13, 14] Performanceoptimizing transformations can also be used at this point [9]. At the end of this step, the simplicity of the common case circuit can be assessed. We also have sufficient information to estimate the power and execution time savings obtainable from the chosen pattern. Step 6 performs this estimate. The process described in the previous paragraph is repeated ....

H. Trickey, "Flamel: A high-level hardware compiler," IEEE Trans. Computer-Aided Design, vol. 6, pp. 259--269, Mar. 1987.

.... subexpression replication and associativity, where the first one acts as an enabling transformation for the second one [Mil88] Associativity, distributivity and commutativity are the three most often used algebraic transformations, commonly treated under the paradigm of tree height reduction [Tri87, Har89, Lob91, Dun92]. When retiming is the only transformation of interest and the goal is the minimization of the critical path, several algorithms designed by Leiserson and Saxe provide an optimal solution in polynomial time [Lei91] When the goal is minimal area or power, the problem has been proven to be ....

H. Trickey. Flamel: A High-Level Hardware Compiler. IEEE Transaction on CAD, Vol.6, (no.2), pp.259-269, 1987.

....language (e.g. C or VHDL) Then software translates the specification into a hardware image and programs the FPGA(s) which implement the fitness function. This softwareto hardware translator could be similar in function to the PRISM II compiler [12] 13] the spC compiler [19] Flamel [20], Cyber [21] or an HDL synthesizer such as IBM s HIS system [22] or AutoLogic from Mentor Graphics [23] Then the front end sends a Go signal to the back end. When the HGA back end detects the signal, it runs the GA based on the parameters already in the shared memory. When done, the back end ....

H. Trickey, "Flamel: A high-level hardware compiler," IEEE Transactions on Computer Aided Design, vol. CAD-6, no. 2, pp. 259--269, March 1987.

....for which speed is the primary objective. In high level synthesis, transformations for throughput and power optimization for data flow intensive (DFI) behavioral descriptions is a well researched problem [8] 9] 10] 11] 12] 13] Transformations for CFI behaviors are considered in [14], 15] 16] In [14] loop merging and loop unrolling are used, followed by a greedy application of tree height reduction and constant propagation. In [15] procedure inlining, redundant code elimination, and pipelining are used. In [16] a tree height reduction technique is presented which can ....

....is the primary objective. In high level synthesis, transformations for throughput and power optimization for data flow intensive (DFI) behavioral descriptions is a well researched problem [8] 9] 10] 11] 12] 13] Transformations for CFI behaviors are considered in [14] 15] 16] In [14], loop merging and loop unrolling are used, followed by a greedy application of tree height reduction and constant propagation. In [15] procedure inlining, redundant code elimination, and pipelining are used. In [16] a tree height reduction technique is presented which can transcend basic block ....

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H. Trickey, "Flamel: A high-level hardware compiler," IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 259--269, Mar. 1987.

....O2 O1 O2 O1 Join Fork Join Fork Join Fork I2 I1 I1 I2 Figure 35: Local Transformation 1. 6. 2 Local Transformations Algorithmic transformations can be used to improve the design efficiency at the behavioral level so that the resulting design description can generate a suitable implementation [27, 29, 31]. Most transformations use the peephole optimization technique, used similarly in the compiler design, and are therefore called local transformations in this context. The biases in behavioral level descriptions are caused by the designers coding style or generated by other transformations such as ....

H. Trickey. "Flamel: A High-Level Hardware Compiler". IEEE Transactions on Computer-Aided Design, 6(2):259--269, March 1987.

....and faster than the single process design and with more potential concurrency . Should the design be pipelined or left unpipelined, and if pipelined, how many stage divisions should there be, and where should they be placed Research into these questions is just beginning. The Flamel system [12] automatically applies loop unrolling and other basic block transformations to improve the parallelism of a design. The Yorktown Silicon Compiler [3] partitions its designs, although its partitioning is performed at the Functional Block Level, and is used primarily to limit the size of the design ....

H. Trickey. Flamel: A High-Level Hardware Compiler. IEEE Transactions on CAD CAD-6(2):259--269, March, 1987.

....on the different facets of the design are used to construct a set of interacting boolean level behavior tables which can be realized using sequential logic synthesis tools (e.g. 1] Many design automation systems use directed acyclic graph (DAG) based structures for design representation. Flamel [2] uses a DAG based representation to model data flow and control flow. Transformations are defined on the DAGs for scheduling and allocation. The System Architect s Workbench [3] also uses a DAG based internal representation called Value Trace. Behavioral and structural transformations are defined ....

H. Trickey, "Flamel: A high-level hardware compiler," in Transactions on Computer-Aided Design 1987, pp. 259--269, IEEE, Mar. 1987.

....machine model. Along with the global view of a design, behavior tables can also provide abstract views of a design. A table form can be a useful visual output for a designer to interact with the design tool. Many design automation systems use graph based structures for design representation [1, 2, 3], which are suited for either control flow or data flow representation. Petri net based internal representations are Research reported herein was supported, in part, by NSF, under grants numbered MIP 89 21842 and MIP 92 08745. y Email: rathk cs.indiana.edu also suited for control flow ....

H. Trickey, "Flamel: A high-level hardware compiler," in TCAD 1987, pp. 259--269, IEEE, Mar. 1987.

....alterations in the computational structure such that the behavior (the relationship between output and input data) is maintained. Transformations are used extensively in several computer science, computer engineering, and CAD areas, most often in compilers [Fis88] and behavioral level synthesis [Sno78, Wal89, Pot91, Tri87]. This section shows how transformations, using specifically tailored optimization techniques, can significantly reduce the area overhead for designs with BISR requirements. 5.1 Key Ideas and Motivational Examples The basic idea behind using transformations in behavioral level synthesis for HBISR ....

H. Trickey, "Flamel: A High-Level Hardware Compiler," IEEE Transactions on CAD, Vol. 6, No. 2, pp. 259269, 1987.

....excellent overwiev of the different schools of thought has been given in [27] The scheduling and allocation are closely interrelated. In order to have an optimal design, both tasks should be performed simultaneously [19] However, due to the time complexity, many systems perform them separately [10,22,26,29,47,49] or introduce iteration loops between the two subtasks [17,32,34,44] Scheduling involves assigning the operation to so called control steps. A control step is the fundamental sequencing unit in synchronous systems; it corresponds to a clock cycle. Different methods for scheduling will be ....

....parallel, which comes form the schedule. Therefore, scheduling and allocation are strongly interdependent tasks. The most straightforward approach to this problem is to set some limit (or no limit at all) on the resource cost and then to schedule, as it is done in systems CMUDA [12,18,49] Flamel [47], and V [5] A more flexible approach is to iterate the whole process changing the resource limits until a satisfactory design has been found. This approach is used in MIMOLA [26,50] and Sehwa [31] Another approach is to develop the schedule and allocation simultaneously, as in systems HAL ....

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Trickey H. (1987) Flamel: A High-Level Hardware Compiler. IEEE Trans. CAD, 6, 2, p. 259-269.

....the data paths [3] Loop pipelining techniques transform a sequential loop into a loop with parallelism across multiple iterations extracted while preserving the program s semantics. Since scheduling with resource constraints in general is NP complete, heuristic based loop pipelining techniques [5, 19, 7] have been developed to compact loops with given resource constraints. Percolation based loop pipelining techniques [18] first compact a loop into its optimal parallel counterpart and then apply resource constraints on the parallel version. Static scheduling via optimum unfolding [16] in DSP ....

....t[14] 3 a[ k 10] k 9] t[25] t[24] 3 a[ k 14] k 13] t[5] t[4] 3 a[ k 7] k 6] t[10] a[ k 8] k 7] 3 a[ k 9] k 8] 4. x[ k 4] x[ k 4] t[3] t[9] t[8] c[ k 7] t[16] t[15] c[ k 10] t[26] t[25] c[ k 14] t[11] t[10] 3 a[ k 10] k 9] t[19] = a[ k 12] k 11] 3 a[ k 13] k 12] 5. x[ k 6] t[4] 3 x[ k 4] x[ k 7] t[5] 3 x[ k 4] t[17] t[16] 3 a[ k 11] k 10] t[27] t[26] 3 a[ k 15] k 14] t[12] t[11] 3 a[ k 11] k 10] t[20] t[19] 3 a[ k 14] k 13] 6. x[ k 6] x[ k 6] t[7] x[ k ....

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H. Trickey, "Flamel: a high-level hardware compiler", IEEE Trans. on CAD, Vol. CAD-6, No. 2, March 1987.

....functions. The function must be optimized to enable synthesizing a circuit with the shortest possible delay. Current optimization techniques that restructure critical paths are based either on optimizing Boolean functions [7, 2, 19, 11] or on exclusively manipulating arithmetic expressions [20, 15, 17, 6]. Optimizing arithmetic and Boolean functions concurrently yields better results than can be achieved by arithmetic optimization followed by Boolean optimization. We present a small example to illustrate the benefits of concurrently optimizing Boolean and arithmetic functions. We assume that the ....

H. Trickey. "Flamel: A High-Level Hardware Compiler". IEEE Transactions on Computer-Aided Design, CAD6 (2):259 --269, March 1987.

....and routers subject to user specified resource constraints. The processors are assumed to be constructed of dynamic memory to memory pipelines. Keywords: Design, methodology, gradient, pipeline, processor, and architecture 1 Introduction Several Computer Aided Design (CAD) 1] 2] 3] [4] tools have been developed for hardware allocation process in design of processors. In this paper, we present a design methodology for allocating hardware resources leading to an optimal design of a pipelined attached processor. The processor is assumed to be constructed of memory to memory ....

....example are given in columns 1 through 4 of Table 1. The t d i was assumed to be 0. The overall setup time, t o was considered to be 100 nanoseconds. The overhead cost, c o was chosen as 3 mm 2 . A run of the optimization procedure produced an architecture with a replication factor vector r = [1 3 1 1 1 1 4 1 1 1 4 1 1 4 6 16 4 1 2 1 1 1 1 1] The architecture suggests a design consisting of a main memory subsytem M 1 , having 1 input bus, 3 memory modules interleaved into 3 banks, and 1 output bus, a memory M 2 having 1 input bus, one bank of 4 memory modules, and 1 output bus, a multiplier subsystem PM , with 4 parallel stages, an ....

H. Trickey, " Flamel: A high level hardware compiler, " IEEE Transactions on Computer Aided Design, Vol. CAD-6, March 1987, pp. 259-69.

.... ENVIRONMENT 124 In high level synthesis, basic interdependent tasks which must be done include translation of the high level language into an internal representation (typically some variation of a graph with control flow and data flow constructs) transformations (at all levels of the process) [124, 102, 89] scheduling, allocation, assignment, as described in [74] Various approaches differ in manner and the order in which these basic tasks are attacked. In one approach, scheduling, allocation and assignment are performed separately and in separate phases. The advantage of this approach is that it ....

H. Trickey. "Flamel: A High-Level Hardware Compiler". IEEE Transactions on Computer Aided Design, CAD-6:259--269, Mar.. 1987.

....1 Introduction Tree height reduction (THR) 1, 12] is a well known technique for reducing the critical path length and increasing the parallelism of expressions and or recurrences through the introduction of redundant computation. THR has been applied to the synthesis of DSP applications [8, 11, 13, 19] and will continue to play an important role in system and architectural level synthesis. The synthesis of memory intensive behaviors has been identified as important for application areas such as image and video algorithms [7, 16, 20] Typically, designs synthesized for memory intensive behaviors ....

....technique uses memory anti aliasing theory so as to detect redundancy in a general manner. Tree Height Reduction Tree height reduction was first studied [1, 12] as a method for reducing critical dependency chains to increase parallelism and was later extended in [3] Various synthesis systems [8, 19] include support for THR, but do not specifically factor resource availability into the process, or do so in an exhaustive manner [11] In [13] an incremental reduction technique is presented which globally (i.e. over multiple expressions in the program) exploits unused resources by factoring ....

H. Trickey. Flamel: A High-Level Hardware Compiler. IEEE Trans. on CAD, 6(2), March 1991.

....are used to exploit parallelism in flow graphs [18] Loop and compiler transformations have attracted most attention in that field [2, 17, 13, 23, 30, 27] They all rely on manual ordering strategies. In high level synthesis, transformations are mainly used for throughput optimisation [16, 5, 9, 25], but are recently also used for power optimisation [4] Using transformations for direct area optimisation has not yet attracted much attention. Local resource utilisation optimisation on primitive building blocks like adders and multipliers has been done using transformations steered by ....

H. Trickey, "Flamel: A high-Level Hardware Compiler," IEEE Trans. on Computer-Aided Design, Vol. 6, No. 2, pp. 259--269, 1987.

....[7] 3.2 Transformations in High level Synthesis Over the last few years, several high level synthesis systems have incorporated comprehensive sets of transformations, coupled with powerful optimization strategies. Example systems with elaborate applications of transformations are Flamel [8], SAW [9] SPAID [10] HYPER [11] and CATHEDRAL [12] Among the set of transformations used by the Flamel design system are loop transformations, height reduction and constant propagation. SAW uses among other transformations in line expansion, dead code elimination, four types of transformations ....

H. Trickey, "Flamel: A high-Level Hardware Compiler", IEEE Transaction on CAD, Vol. 6, No. 2, pp. 259-269, 1987.

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Trickey 87 H. Trickey, "Flamel: A High-Level Hardware Compiler," IEEE Transactions on CAD, Vol. CAD-6, No. 2, pp. 259-269, March, 1987.

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H. Trickey. Flamel: A High-Level Hardware Compiler. Transactions on CAD CAD-6(2):259-269, March, 1987.

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