Ellis, J.R.: A Compiler for VLIW Architectures. PhD thesis, Yale University (1984)  Home/Search   Document Not in Database   Summary   Related Articles   Check

....delayed. To minimize the execution time and to fully utilize the registers, instruction scheduling and register allocation must be considered at the same time. Several heuristics have been proposed to solve register allocation and instruction scheduling together. For example, the strategy used in [6, 8, 23] is to keep the information on the next use of each register. The register whose next use is the farthest is spilled if there are not enough registers. In [22] a graph combining the control data flow graph and the register interference graph was proposed to solve the two optimizations ....

J.R. Ellis, A Compiler for VLIW Architectures, MIT Press, Cambridge, (1986).

.... predicated execution [8] numerous techniques to reduce instruction penalties [14] and the concurrent execution of more than one thread of control [9] 13] Current improvements in the field of scheduling techniques are: an enlargement of the program sections treated by the algorithms [1] 4][6][17] the improvement of the used heuristics [5] the enhancement of the information made available by dataflow analysis [11] and a better exploitation of the processor properties [21] Neither the above mentioned improvements of scheduling techniques nor hardware techniques that implement some ....

....time of the program decreases. Conditional branches seriously prevent the scheduling techniques from moving instructions to unused instruction slots. Whether a conditional branch is taken or not cannot be decided during compile time. Global scheduling techniques as for instance trace Scheduling [6], PDG Scheduling [1] Dominator path Scheduling [17] or Selective Scheduling [10] use various approaches to overcome this problem. However, investigations have shown that the conditions that must be fulfilled to safely move an instruction across the basic block boundaries are very restrictive. ....

J. R. Ellis. A Compiler for VLIW Architectures. The MIT Press, Cambridge, MA, 1986.

....zero or low cost is guaranteed. 8 Conclusions and Ongoing Work Code generation for irregular datapaths and machines with severely restricted instruction sets, such as those used in DSP and embedded microprocessors, is a problem that has received relatively little attention to date. Previous work [4, 5, 7, 11] on VLIW machines, microcode generation and application specific instruction processors has covered the topic of irregular data paths but restricted addressing and code density has never been their primary concern. Liem et al. 10] presented techniques for generating compact code; however, the ....

John R. Ellis. A Compiler for VLIW Architectures. MIT Press, 1985.

....work in generating code for partitioned register banks. We then describe our method, detail an experiment studying value cloning and finish with our conclusions. 2 Previous Work Ellis described the first solution to the problem of generating code for partitioned register banks in his dissertation [2]. His method, called BUG (bottom up greedy) is applied to a scheduling context at a time This research has been partially supported by Texas Instruments and NSF grant CCR 980781. y Digital Equipment Corporation, 110 Spit Brook Road (ZK02 3 N30) Nashua NH 03062. z Department of Computer ....

Ellis, J. A Compiler for VLIW Architectures. PhD thesis, Yale University, 1984.

.... [10] predicated execution [11] forwarding techniques to reduce instruction penalties [10] and the concurrent execution of more than one thread of control [12] Current improvements in the field of scheduling techniques are: an enlargement of the program sections treated by the algorithms [1] 4][6][19] an improvement of the used heuristics [5] an enhancement of the information made available by dataflow analysis [14] and a better exploitation of the processor properties [23] The improvements of scheduling techniques mentioned above and the hardware techniques that implement some kind of ....

....time of the program decreases. Conditional branches seriously prevent the scheduling techniques from moving instructions to unused instructions slots. Whether a conditional branch is taken or not cannot be decided during compile time. Scheduling techniques as for instance Trace Scheduling [6], PDG Scheduling [1] Dominator path Scheduling [19] or Selective Scheduling [13] use various approaches to overcome this problem. However, investigations have shown that the conditions that must be fulfilled to safely move an instruction across the basic block boundaries are very restrictive. ....

J. R. Ellis. A Compiler for VLIW Architectures. The MIT Press, Cambridge, MA, 1986.

....We call this technique register component graph partitioning, since the nodes of the graph represent virtual registers appearing in the program s intermediate code. 2. Previous Work Ellis described the first solution to the problem of generating code for partitioned register banks in his thesis [6]. His method, called BUG (bottom up greedy) is applied to a scheduling context at a time (e.g. a trace) His method is intimately intertwined with instruction scheduling and utilizes machine dependent details within the partitioning algorithm. Our method abstracts away machine dependent details ....

J. Ellis. A Compiler for VLIW Architectures. PhD thesis, Yale University, 1984.

....proves to be effective in further increasing the code density. Code generation for irregular data paths and machines with severely restricted instruction sets, such as those used in DSP and embedded microprocessors, is a problem that has received relatively little attention to date. Previous work [5, 6, 8, 12] on VLIW machines, microcode generation and application specific instruction processors has covered the topic of irregular data paths but restricted addressing and code density has never been their primary concern. Liem et al. 11] presented techniques for generating compact code; however, the ....

John R. Ellis. A Compiler for VLIW Architectures. MIT Press, 1985.

....definition can still lead to non optimal code when dynamic instruction count is taken into account. In general, basic block based scheduling suffers from the limited ability to discover opportunities for inter block optimization. Therefore, we propose using trace scheduling based techniques [3, 4]. Given a data flow graph, we select a trace, which is the most probable sequence of basic blocks, and perform optimal scheduling on the trace as though it were a basic block. This process is repeated until all basic blocks in the flow graph have been scheduled. Instructions necessary to set the ....

John R. Ellis. A Compiler for VLIW Architectures. MIT Press, 1985.

.... execution, predicated execution [10] numerous techniques to reduce instruction penalties, and the concurrent execution of more than one thread of control [12] Current improvements in the field of scheduling techniques are: an enlargement of the program sections treated by the algorithms [1] 4][6][21] the improvement of the used heuristics [5] the enhancement of the information made available by dataflow analysis [14] and a better exploitation of the processor properties. Neither the above mentioned improvements of scheduling techniques nor hardware techniques that implement some kind ....

....execution time of the program decreases. Conditional branches seriously prevent the scheduling techniques from finding a good solution. It is generally impossible to decide during compile time whether a conditional branch is taken or not. The different scheduling techniques (e.g. Trace Scheduling [6], PDG Scheduling [1] Dominator path Scheduling [21] or Selective Scheduling [13] use various approaches. However, investigations have shown that the conditions that must be fulfilled to safely move an instruction across the basic block boundaries are very restrictive. Therefore the scheduling ....

J. R. Ellis. A Compiler for VLIW Architectures. The MIT Press, Cambridge, MA, 1986.

....algorithms obtain substantial improvements in code size and performance over conventional code generation techniques. We are currently developing a framework for retargetable code generation [9] There are many avenues for further work in this area. Our framework is directly applicable to traces [4][5] rather than just basic blocks, and experiments on traces will be conducted in the near future. Traces will allow for more global optimization and afford the possibility of even greater savings over conventional optimization. One way to avoid the possible code explosion caused by trace ....

John R. Ellis. A Compiler for VLIW Architectures. MIT Press, 1985.

No context found.

Ellis, J.R.: A Compiler for VLIW Architectures. PhD thesis, Yale University (1984)

No context found.

Ellis, J.R.: A Compiler for VLIW Architectures. PhD thesis, Yale University (1984)

No context found.

J. R. Ellis. A Compiler for VLIW Architectures. PhD thesis, Yale University, 1984.

No context found.

J. R. Ellis. A Compiler for VLIW Architectures. PhD thesis, Yale University, 1984.

No context found.

J. R. Ellis. A Compiler for VLIW Architectures. PhD thesis, Yale University, 1984.

No context found.

J. Ellis. A Compiler for VLIW Architectures. PhD thesis, Yale University, 1984.

No context found.

J. R. Ellis. A Compiler for VLIW Architectures. PhD thesis, Yale University, 1984.

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