J.R. Burch, E.M. Clarke, D.L. Dill, and K. McMillan, "Sequential circuit verification using symbolic model checking," in Proc. Design Automation Conference (DAC), pp. 46--51, Orlando, FL, June 1990.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....and CCR 0219805 (ITR Program) The authors wish to thank Ulrich Stern and Prof. David Dill for making available the source code of Parallel Murphi on which our tool is based. The states can be symbolically represented, such as representing states using a Binary Decision Diagram (BDD) [BCMD90]. This is called symbolic model checking. Both methods have domains where they outperform each other. The properties that are verified can also be classified into two categories: Safety properties. In plain English, these are properties that say that something bad never happens . ....

J.R. Burch, E.M. Clarke, K.L. McMillan, D.L.Dill, "Sequential circuit verification using symbolic model checking", in 27th ACM/IEEE Design Automation Conference, pp. 46-51, 1990.

....the BDD ADD data structures that enable efficient manipulation of large and complex Boolean and pseudo Boolean functions. More specifically, the symbolic kernel extraction algorithm we present in Section VI exploits well established technology developed in the context of FSM reachability analysis [5] [8] to extract kernels for FSMs that are too large to be handled by explicitly enumerative algorithms. Unfortunately, large sequential components, which are the most common ones in the design practice, are often beyond the capabilities of the most powerful algorithms based on symbolic ....

J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill, "Sequential circuit verification using symbolic model checking," in Proc. ACM/IEEE Design Automation Conf., Orlando, FL, June 1990, pp. 46--51.

....#R (#x, #z)# S (#z, #y) # where R S denotes the composition of relations R and S. Quantification over a variable vector involves quantifying over each of the vector elements in any order. Taking this further, we can compute the transitive closure of a relation using fixed point techniques [Burch et al. 1990a] The function #R # is computed as the limit of a sequence of functions #R i , each defining a relation: R 0 = I R i 1 = I R i where I denotes the identity relation. The computation converges when it reaches an iteration i such that #R i = #R i 1 , again making use of efficient ....

....a graph, with a vertex for each element in A, and an edge for each element in R, then the relation R i denotes those pairs reachable by a path with at most i edges. Thus, the computation must converge in at most 1 iterations, where = A . A technique known as iterative squaring [Burch et al. 1990a] reduces the maximum number of iterations to n = #. Each iteration computes a relation R (i) denoting those pairs reachable by a path with at most 2 i edges: R (0) I R (i 1) R (i) R (i) Many applications of OBDDs involve manipulating relations over very large sets, and hence ....

[Article contains additional citation context not shown here]

Burch, J. R., Clarke E. M., Dill, D. L., and McMillan, K. 1990. Sequential circuit verification using symbolic model checking. Proceedings of the 27th ACM/IEEEDesign Automation Conference (Orlando, June) ACM, New York, pp. 46--51. 31

....only. The work presented in this paper provides the semantical basis for rigorous and complete consistency checks between the descriptive view of the system by sequence charts and the constructive one. Such checks could eventually be made using formal verification techniques like modelchecking [3, 4]. Some of the ideas of this paper were indeed inspired by the symbolic timing diagrams of [16, 31 33] used to specify and verify safety critical requirements for systems modeled using Statemate; see [8, 9, 11, 12, 24] The paper is organized as follows. Section 2 defines the way we link LSC ....

J.R. Burch, E.M. Clarke, K.L. McMillan, and D.L. Dill, "Sequential circuit verification using symbolic model checking," in Proc. 27th ACM/IEEE Design Automation Conference, 1990, pp. 46--51.

....transition relation. In model checking approaches that are based on decision diagrams (e.g. BDDs and MDGs) the transition relation of a transition system that is to be checked should be partitioned and represented by smaller graphs rather than represented and treated as one large graph (c.f. BCMD90] Partitioning helps prevent the (single) representing graph growing too big. Instead of working with one graph for representing the whole transition relation, the algorithms work on a set of smaller graphs, each representing a part of the transition relation only. This technique is adapted for ....

J. Burch, E. Clarke, K. McMillan, and D. Dill. Sequential circuits verification using symbolic model checking. In Proc. of 27th ASM/IEEE Design Autiomation Conference, 1990.

....can increase the accuracy of the power estimate by calculating the static probabilities of the present state lines more accurately. Techniques to compute the reachable set of states, or the strongly connected portion of the STG of a sequential machine, can be developed, based on the strategies of [9, 4]. These techniques are viable for machines with up to approximately 50 flip flops. Thereafter, the static probability of each present state line can be calculated. For example, if a machine has states 00, 01, and 10, and it is in these states with proabilities 0.1, 0.5, 0.4, respectively, then the ....

J. Burch, E. Clarke, K. McMillan, and D. Dill. Sequential Circuit Verification Using Symbolic Model Checking. In Proceedings of the 27 h De- sign Automation Conference, pages 46-51, June 1990.

....of our solution formulas. The iterative interpretation of quantitative game calculus leads to algorithms for the computation of approximate solutions. By representing value functions symbolically, these algorithms may be used for the approximate analysis of games with very large state spaces [BMCD90, dAKN 00] Unfortunately, except for safety and reachability conditions, the alternance of least and greatest fixpoint operators in the solution formulas leads to approximation schemes that do not converge monotonically to the value of a game. This situation contrasts with the one for Markov ....

J.R. Burch, K.L. McMillan, E.M. Clarkes, and D.L. Dill. Sequential circuit verification using symbolic model checking. In Proc. of the 27th ACM/IEEE Design Automation Conference, pages 46--51, Orlando, FL, USA, June 1990.

.... pass variables, respectively [28] Existing methodologies for implementing PTL networks are limited to two level synthesis procedures [27] 28] Binary decision diagrams (BDD s) 2] 9] have been used for synthesizing and analyzing combinational as well as sequential circuits [1] 4] 5] [7], 8] 15] We have shown [11] that BDD s are not well suited for synthesizing area efficient PTL networks. In this paper, we develop a model for PTL networks which we call the 123 decision diagram (123 DD) model, and we have investigated multilevel logic synthesis techniques for PTL networks ....

J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill, "Sequential circuit verification using symbolic model checking," in Proc. 27th IEEE/ACM Design Automat. Conf., 1990, pp. 46--51.

....that the number of states grows generally exponentially with the number of storage elements which is known as the state explosion problem. This remains a problem even if states and transition relation are represented symbolically by decision diagrams usually OBDDs as in symbolic model checking [9], i.e. traversal leads for many designs to graph explosion or long computation times. Various techniques exist to tackle these problems which allow pushing the limit further (e.g. by state reduction [16] but either do not provide a general solution for fast automatic traversal of large circuits ....

J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill. Sequential circuit verification using symbolic model checking. In DAC'90, 1990.

....in section 6. Experimental results are presented in section 7. Finally, section 8 gives a conclusion. 2 Related Work Various representations for memory operations have been proposed for formal verification of designs with complex control. States are represented by decision diagrams in [4] for traversing an automata for model checking and in [3] for equivalence checking. This permits the representation of a register file, but not, e.g. of a large data memory due to the sensitivity to graph explosion. 14] uses decision diagrams combined with an encoding technique to represent ....

J. R. Burch, E. Clarke, K. McMillan, and D. Dill. Sequential circuit verification using symbolic model checking. In DAC'90, 1990.

....systems are often specified in a more restricted way. For example, they are often finite state. Many safety properties (including deadlock detection) can be detected in a time independent way using existing model checking and language containment methods (see, e.g. Kurshan [53] and Burch et al. [54]) Unfortunately, verifying most temporal properties is much more difficult (Alur and Henzinger [55] provide a good summary) Much more research is needed before this is practical. 376 PROCEEDINGS OF THE IEEE, VOL. 85, NO. 3, MARCH 1997, PP. 366 390 A. Simulation Simulating embedded systems is ....

.... supports composition and abstraction (hiding of edge labels) Moreover, self bisimulation is an equivalence relation among states of an automaton, and hence it can be used to minimize the automaton (the result is called the quotient automaton) In model checking (see, e.g. 70] 71] [54], 6] the system is modeled as a synchronous or asynchronous composition of automata, and the property is described as a formula in some temporal logic [72] 73] The proof is again carried out by traversing the state space of the automaton and marking the states that satisfy the formula. ....

J. Burch, E. Clarke, K. McMillan, and D. Dill, "Sequential circuit verification using symbolic model checking," in Proc. of the Design Automation Conf., 1990, pp. 46--51.

....terminations. The CNF formulas were tested using GRASP. The experiments were conducted on a 333 MHz Pentium Pro running Linux and equipped with 512 MByte of RAM. In order to measure the performance difference between SAT based and BDD based approaches, we modeled the PCI specification in SMV [4] and tested the same properties using CTL model checking. We used Carnegie Mellon s SMV [4] as the model checker. The SAT based approach was able to verify the protocol within 2 minutes using up to 3.5 MByte of memory. The BDD based approach required 112 minutes of CPU and up to 27MByte of RAM. ....

....on a 333 MHz Pentium Pro running Linux and equipped with 512 MByte of RAM. In order to measure the performance difference between SAT based and BDD based approaches, we modeled the PCI specification in SMV [4] and tested the same properties using CTL model checking. We used Carnegie Mellon s SMV [4] as the model checker. The SAT based approach was able to verify the protocol within 2 minutes using up to 3.5 MByte of memory. The BDD based approach required 112 minutes of CPU and up to 27MByte of RAM. The above experiment uncovered several errors in the PCI specification that were previously ....

J. Burch, E. Clarke, K. McMillan, and D. Dill, "Sequential circuit verification using symbolic model checking," in Proc. of the 27th ACM/IEEE Design Automation Conference, 1990.

....using the well established approach of hierarchically organized state machines. We strive for a verification approach which is compositional w.r.t. the decomposition of systems into subsystems. This will allow activities of reasonable complexity to be verified using symbolic model checking [5, 4, 19]. Larger activities will be verified on the basis of proof systems relating properties of individual activities to properties of compound activities, using the well known assumption commitment paradigm [1, 21, 15] A key topic for this paper is the construction of so called compositional models, ....

J.R. Burch, E.M. Clarke, K.L. McMillan, and D.L. Dill. Sequential circuit verification using symbolic model checking. In ACM/IEEE Design Automation Conference, June 1990.

....a single sequence of states augmented with a limited set of loops. In our work, trajectory assertions are general state diagrams. We have extended STE to deal with generalized trajectory assertions. Our work has some resemblance to the capabilities provided by the Symbolic Model Verifier (SMV)[5][6] SMV requires a closed system. The environment is modeled as a set of machines. In some sense the state diagrams in our mapping correspond to creating an environment around the system. The state diagrams corresponding to the inputs can be viewed as generators that generate low level signals ....

J. R. Burch, E. M. Clarke, K. L. McMillan and D. L. Dill, "Sequential Circuit Verification Using Symbolic Model Checking," 27th Design Automation Conference, pp. 46-51, June 1990.

....classified in enumerative methods and symbolic methods. Enumerative methods operate on states as the basic entities [4, 17] and represent sets of states and transition relations in terms of the individual states. Symbolic methods operate directly on symbolic representations of sets of states [3, 2]. Our approach to the model checking of the Web is enumerative, in that we represent sets of Web pages as collections of single pages. However, we argue that it is convenient to phrase our model checking algorithms as symbolic algorithms, based on the manipulation of sets of Web pages. In fact, a ....

J.R. Burch, K.L. McMillan, E.M. Clarkes, and D.L. Dill. Sequential circuit verification using symbolic model checking. In Proc. of the 27th ACM/IEEE Design Automation Conference, pages 46--51, Orlando, FL, USA, June 1990.

....if; DONE = 1 ; end case; end process; end BEHAVIOR; Figure 1: VHDL description of a simple example identification and manufacturing test. The approach in [11] also targets part of the state space in a manner very similar to ours and uses the counterexample facility in the SMV model checker [4] to generate a test for each transition in the targeted state space. However, mapping this test to the actual machine depends on recognition of patterns of high level behavior in the generated test sequence and is a labor intensive process. In addition, there exist ad hoc techniques for coverage ....

....AND operation. ffl T 2 ( Q) 9 x; q T 1 ( x; q; Q) ffl Finally the next state variables in T 2 are substituted with the present state variables, using the composition operation. The first two steps can be efficiently performed using the elegant method developed by Clarke et al. [4]. The well known algorithm for computing reachable states is described in Figure 6. Given a set of present states, the set of states reachable in one step is computed as the Image of the next state function ffi over the subdomain given by the present states. The set of the newly reached states is ....

J. Burch, E. Clarke, K. McMillan, and D. Dill. Sequential circuit verification using symbolic model checking. Proc. 27th DAC, pages 46--51, 1990.

....automation comunity has seen whole new areas emerge in the last decade. High level synthesis [Ber93] has allowed a higher level of abstraction in the design process and has become mainstream. Formal verification methods [CW96] such as theorem proving, equivalence checking and model checking [BCMD90]) aim to prove the correctness of the designs and commercial tools are now available. This research is sponsored by the Centro Nacional de Pesquisa (CNPq) under Iniciac ao Cientfica (IC) and Programa Tematico Multi institucional em Ciencia da Computac ao (ProTem CC) programs. Any opinions, ....

J.R. Burch, E.M. Clarke, K.L. Mc Millan, and D.L. Dill. Sequential circuit verification using symbolic model checking. In 27th ACM/IEEE Design Automation Conference, DAC'90, 1990.

....circuit. Additionally, we employ the same abstraction techniques to address the problems of redundancy identification and manufacturing test. The approach in [15] also targets part of the state space in a manner very similar to ours and uses the counterexample facility in the SMV model checker [6] to generate a test for each transition in the targeted state space. However, mapping this test to the actual machine depends on recognition of patterns of high level behavior in the generated test sequence and is a labor intensive process. In addition, there exist ad hoc techniques for coverage ....

....in the formal system. These are the theorem proving based approaches [22, 23, 31, 30] These techniques are very powerful in handling abstractions and hierarchical designs but require a high degree of expertise and are not completely automated. State based approaches like symbolic model checking [6] and its variations [33] and language containment [16, 25] are highly automated and more likely to be accepted in the design community. The main drawback of symbolic model checking is the fact that temporal logic formulas can become very complex and difficult to understand. In the language ....

[Article contains additional citation context not shown here]

J. Burch, E. Clarke, K. McMillan, and D. Dill. Sequential circuit verification using symbolic model checking. Proc. 27th DAC, pages 46--51, 1990.

....as in the classical case. 5 Polynomial Expressions Decision diagrams (DD) are a family of data structures originally developed for efficient representation and manipulation of Boolean formulas, but now successfully used for many purposes in computer science, in particular in circuit design tools [15]. Many valued decision diagrams can be computed with the help of a generalized Shannon expansion: 8 : switch p case 0 : fp=0g; case 1 n 1 : fp= 1 n 1 g; case 1 : fp=1g (9) It is based on an (n 1) ary switch connective in n valued logic ....

J. Burch, E. Clarke, K. McMillan, and D. Dill. Sequential circuit verification using symbolic model checking. In Proc. 27th ACM/IEEE Design Automation Conference (DAC), pages 46--51. ACM Press, 1990.

....user guidance and a successful inductive proof is automatically generated. 7 Related Work There has been considerable interest in verifying properties of hardware circuits at the input output level. Many papers on this topic have appeared in conference proceedings and journals[19] to cite a few [7, 9, 12, 17, 21, 10, 16, 34]. Different approaches have been proposed in the literature, notably among them state based approaches and the use of model checkers [9, 7] induction based approaches adapted from software verification [17, 18] and approaches based on modeling hardware circuits using higher order logics [10, 21] ....

....circuits at the input output level. Many papers on this topic have appeared in conference proceedings and journals[19] to cite a few [7, 9, 12, 17, 21, 10, 16, 34] Different approaches have been proposed in the literature, notably among them state based approaches and the use of model checkers [9, 7], induction based approaches adapted from software verification [17, 18] and approaches based on modeling hardware circuits using higher order logics [10, 21] Verifications of ripple carry adders has also been reported using theorem proving and state based 18 systems in [14, 11, 4, 17, 35, 1] ....

J. R. Burch, E.M. Clarke, K. L. Mcmillan and D.L. Dill, "Sequential Circuit Verification using symbolic model checking", in proceedings of Twenty seventh ACM/IEEE Design Automation Conference, 1990.

....components. In general, this can not be circumvented, and for this reason, there is a strong interest in algorithms that can traverse large state sets. A successful approach is known as symbolic model checking. This technique has been independently developed by Burch, Clarke, McMillan, and Dill [6, 8, 9, 7], and by Berthet, Coudert, and Madre [3] both were inspired by [1] We give in this section a brief explanation of the basics of symbolic calculus model checking. The next subsection is concerned with the use of ordered binary decision diagrams as the key data structure for these algorithms; ....

J.R. Burch, E.M. Clarke, K.L. McMillan and D.L. Dill. Sequential Circuit Verification Using Symbolic Model Checking. In ACM/IEEE Design Automation Conference (DAC), pages 46--51, Los Alamitos, CA, June 1990. ACM/IEEE, IEEE Society Press.

....Seger[3] extended STE to perform fixed point computations to verify a single sequence of states augmented with a limited set of loops. We have extended STE to deal with arbitrary state diagrams. Our work has some resemblance to the capabilities provided by the Symbolic Model Verifier (SMV)[5][6] SMV requires a closed system. The environment is modeled as a set of machines. The state diagrams in our mapping correspond to creating an environment around the system. However, there is one essential difference. Though SMV does provide the capability of describing the environment, it does ....

J. R. Burch, E. M. Clarke, K. L. McMillan and D. L. Dill, "Sequential Circuit Verification Using Symbolic Model Checking," 27th Design Automation Conference, pp. 4651, June 1990.

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J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill. Sequential circuit verification using symbolic model checking. In Proceedings of the 27th Design Automation Conference, pages 46--51. IEEE Computer Society Press, June 1990.

No context found.

J. R. Burch, E. M. Clarke, K. L. McMillan, D. L. Dill, "Sequential circuit verification using symbolic model checking", Proc. 27th ACM/IEEE Design Automation Conf., June 1990.

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J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill. Sequential circuit verification using symbolic model checking. In 27th ACM/IEEE Design Automation Conference, 1990.

....its application. 1 Introduction With the increasing cost and complexity of hardware designs and protocols, formal verification techniques become ever more attractive. Boolean decision diagrams (BDDs) 3] have enabled much progress in this area, from the early work applying BDDs to verification [1, 6, 5, 8, 19] through the current work of numerous researchers. Most of the current research on automatic formal hardware verification has focused on gate and transistor level design. We believe that automatic formal verification also has an important role at the very high level of design, for example, in ....

....leading to a state not in I, and, if there is such a path, to output that path as a counterexample to the property being verified. The usual approach to such a verification task is to compute the set of states reachable from S and to check that the set of reachable states is a subset of I (e.g. [8, 5, 7, 19, 4]) This approach entails computing the set of reachable states as the fixed point Z:u:S(u) 9v[Z(v) ffi (v; u) which is the smallest set Z such that S Z and any state that is a successor under ffi of a state in Z is also in Z [6] We will call this approach forward traversal. The ....

J.R. Burch, E.M. Clarke, K.L. McMillan, and David L. Dill, "Sequential Circuit Verification Using Symbolic Model Checking," 27th ACM/IEEE Design Automation Conference, 1990, pp. 46-51.

....verification is attracting increasing interest as a tool to deal with the ever increasing cost and complexity of hardware designs and protocols. Binary decision diagrams (BDDs) 3] have enabled much of the recent progress in this area, starting from the early work applying BDDs to verification [1, 6, 5, 11, 24] and continuing through the current work of many researchers. Current research on automatic formal hardware verification has focussed mainly on gate and transistor level design. We believe that automatic formal verification also has an important role at the very highest levels of design, for ....

....reach a state in Z , and BackImage gives the set of states that in one transition must end up in Z . These image operators form the basic operations of BDD based verification algorithms. If Z and ffi are both represented by small BDDs, these operations can be done directly using BDD operations [6, 5, 24]. If the BDD for ffi is too large to build (a common problem) a number of techniques are available to compute these images without building the BDD for ffi [4, 18] Also, note that BackImage(ffi; Z) PreImage(ffi; Z) so if Z is represented by a small BDD, computing either of these two images ....

[Article contains additional citation context not shown here]

J.R. Burch, E.M. Clarke, K.L. McMillan, and David L. Dill, "Sequential Circuit Verification Using Symbolic Model Checking," 27th ACM/IEEE Design Automation Conference, 1990, pp. 46-51.

....simplibel return a U0 that is weaker than it could be if it had to be a subset of A0. We are still experimenting with ideas for balancing these issues more efficiently. 4 Experimental Results In this section, we describe empirical results for applying our verification method to a pipelined ALU [5] and a subset of the DLX processor [14] 4.1 Pipelined ALU The 3 stage pipelined ALU we considered (figure 3) has been used as a benchmark for BDD based verification methods [3, 4, 5, 6] A natural way to compare the performance of these methods is to see how the CPU time needed for veri ....

....Results In this section, we describe empirical results for applying our verification method to a pipelined ALU [5] and a subset of the DLX processor [14] 4. 1 Pipelined ALU The 3 stage pipelined ALU we considered (figure 3) has been used as a benchmark for BDD based verification methods [3, 4, 5, 6]. A natural way to compare the performance of these methods is to see how the CPU time needed for veri fication grows as the pipeline is increased in size by (for example) increasing its datapath width w or its register file size r. For Burch, Clarke and Long [4] the CPU time grew roughly ....

J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill. Sequential circuit ver- ification using symbolic model checking. In 27th AUM/IEEE Design Automation Uonference, 1990. 12

....4. AG Send # A(Send U Recv) if Send holds, then eventually Recv is true, and until that time, Send remains true. The final task of verification is an automatic process. Every CTL formula has a fixed point characterization that can be used to find the set of states satisfying the formula [3]. 3 PCI Local Bus The PCI Local Bus [12, 13, 14] is a high performance, synchronous bus architecture that can transfer 32 bit or 64 bit data. Its primary goal is to establish an industry standard and optimize for direct silicon (component) interconnection with minimum glue logic required. It ....

J. R. Burch, E. M. Clarke, K. L. McMillan, D. L. Dill, "Sequential circuit verification using symbolic model checking", Proc. 27th ACM/IEEE Design Automation Conf., June 1990.

....sufficiently. Experience indeed shows that bugs can show up after extensive testing, illustrated by numerous bugs in microprocessor designs, including the Pentium bug [21] Applying the same approaches to formal verification as on the high level models is infeasible. Model checking techniques [8, 7, 6] rely on either being able to separate the control from the datapath to avoid a state explosion due to the values in the datapath, or to abstract the datapath to a few state bits. However, there is no effective of developing a specification of the control alone. Furthermore, abstractions of the ....

J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill. Sequential circuit verification using symbolic model checking. In 27th ACM/IEEE Design Automation Conference, 1990.

....expand as quickly as an explicit list of states. One such data structure is the binary decision diagram (BDD) which gives a compact representation for a Boolean function [Bry86] These data structures have proven especially efficient in many cases. Using the paradigm of symbolic model checking, [BCMDH90, BCMD90] we can efficiently perform the computations specified below. An expression for the maximum relation satisfying the simulation condition (SR1 in Definition 1) on a safety simulation relation is: Z:s 1 ; e; s 2 Theta Z(s 1 ; e; s 2 ) 8s 0 1 ; e 0 Theta N 1 (hs 1 ; ei; hs 0 1 ; e 0 ....

J.R. Burch, E.M. Clark, K.L. McMillan, and David L. Dill, "Sequential Circuit Verification Using Symbolic Model Checking," 27th ACM/IEEE Design Automation Conference, 1990, pp. 46-51.

....protocols and circuit designs [4] Use of binary decision diagrams (BDDs) 5] led to an even greater increase in size. Representing transition relations implicitly using BDDs made it possible to verify examples that would have required 10 20 states with the original version of the algorithm [7]. Refinements of the BDD based techniques [6] have pushed the state count up over 10 100 states. In this paper, we show that by combining model checking with abstraction, we are able to handle even larger systems. In one example, we are able to verify a pipelined ALU circuit with 64 registers, ....

....is set to the value of start. Otherwise, if the counter is not zero, it is decremented. The alarm output is set to one when count is zero, and to zero if count is nonzero. 6. 2 The model checker The model checker is essentially a propositional CTL model checker (as described by Burch et al. [7]) extended with a notion of types. While state components need not be only boolean, but they are restricted to finite domains. The model checker knows about all of the types allowed by the compiler. Integers are handled via two s complement representation. When we write temporal logic formulas in ....

J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill. Sequential circuit verification using symbolic model checking. In Proceedings of the 27th Design Automation Conference, pages 46--51. IEEE Computer Society Press, June 1990.

No context found.

J.R. Burch, E.M. Clarke, D.L. Dill, and K. McMillan, "Sequential circuit verification using symbolic model checking," in Proc. Design Automation Conference (DAC), pp. 46--51, Orlando, FL, June 1990.

No context found.

J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill. Sequential circuit verification using symbolic model checking. In Proceedings of the 27th ACM/IEEE Design Automation Conference, pages 46--51. IEEE Computer Society Press, June 1990.

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J.R. Burch, E.M. Clarke, K.L. McMillan, D.L. Dill: "Sequential circuits verification using symbolic model checking", Proc. 27th Design Automation Conf., IEEE CS Press, 1990

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J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill. Sequential circuit verification using symbolic model check- ing. In 27th Design Automation Conference (DAC '90), pages 46--51, 1990.

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J. Burch, E. Clarke, K. McMillan, and D. Dill. Sequential circuit verification using symbolic model checking. In Design Automation Conf., pages 46--51, 1990.

No context found.

J.R. Burch, E.M. Clarke, K.L. McMillan, and D.L. Dill. Sequential circuit verification using symbolic model checking. In Design Automation Conf., pages 46--51, 1990.

No context found.

J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill. Sequential circuit verification using symbolic model checking. In 27th Design Automation Conference (DAC '90), pages 46--51, 1990.

No context found.

J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill, "Sequential Circuit Verification Using Symbolic Model Checking," 27th Design Automation Conference, 1990, pp. 46--51.

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J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill. Sequential circuit verification using symbolic model checking. In 28th Design Automation Conference, 1991.

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J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill. Sequential circuit verification using symbolic model checking. In Proc. Design Automation Conference, pages 46--51, 1990.

No context found.

J. R. Burch, E. M. Clarke, D. L. Dill, and K. McMillan, "Sequential Circuit Verification using Symbolic Model Checking, " 27th Design Automation Conference, June, 1990.

No context found.

J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill. Sequential circuit verification using symbolic model checking. In 27th Design Automation Conference (DAC '90), pages 46--51, 1990.

No context found.

J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill, "Sequential circuit verification using symbolic model checking," 27th Design Automation Conference, 1990.

No context found.

J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill, "Sequential Circuit Verification Using Symbolic Model Checking," 27th Design Automation Conference, 1990.

No context found.

J. Burch, E. Clarke, K. McMillan, and D. Dill. Sequential circuit verification using symbolic model checking. In Proceedings of the Design Automation Conference, pages 46--51, 1990.

No context found.

J. Burch, E. Clarke, K. McMillan, and D. Dill. "Sequential Circuit Verification Using Symbolic Model Checking". Proc. 27th DAC, pages 46--51, 1990.

No context found.

J. Burch, E. Clarke, K. McMillan, and D. Dill. "Sequential Circuit Verification Using Symbolic Model Checking". Proc. 27th DAC, pages 46--51, 1990. 13

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J. Burke, E. Clarke, K. McMillan and D. Dill, "Sequential Circuit Verification using Symbolic Model Checking", Proceedings of the 27th IEEE Design Automation Conference, pp. 46-51, 1990. 18

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