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S. Hily and A. Seznec. Contention on 2nd level cache may limit the effectiveness of simultaneous multithreading. Technical Report PI-1086, IRISA, February 1997. 148

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Standard Memory Hierarchy Does Not Fit Simultaneous.. - Hily, Seznec (1998)   (3 citations)  Self-citation (Hily Seznec)   (Correct)

....predicted. Figure 1 illustrates the simulated architecture. Our fetch mechanism is able to select several instructions from each thread for the execution. If a single thread is available, it has the opportunity to fill all slots in the execution pipeline. This mechanism is fully described in [8]. 3 Methodology We performed simulations by varying memory hierarchy parameters while executing 1, 2, 4 or 6 threads simultaneously. Distinct programs are assigned to the threads in the processor. For each simulation, we warm the memory hierarchy with the execution of 1 million instructions per ....

....4.1 Contention on L2 cache on simultaneous multithreading This section explores the impact of contention on performance when executing several threads simultaneously. A similar study had been conducted for singlethreaded workloads to provide data on the different applications used. Its results [8], were used to create groups of benchmarks exhibiting various behaviors : high, low or medium memory pressure, high, low or medium cpu activity, We then simulated different conventional configurations of memory hierarchy while executing several threads together. Figure 2 shows the average ....

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S. Hily and A. Seznec. Contention on 2nd Level Cache May Limit the Effectiveness of Simultaneous Multithreading. TR IRISA-1086, February 1997.


Exploiting Thread-Level Parallelism On . . . - Lo (1998)   (Correct)

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S. Hily and A. Seznec. Contention on 2nd level cache may limit the effectiveness of simultaneous multithreading. Technical Report PI-1086, IRISA, February 1997. 148


Memory Subsystem Design for Multithreaded Processors - Florin Baboescu Dean   (Correct)

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S. Hily and A. Seznec. Contention on 2nd level cache may limit the effectiveness of simultaneous multithreading. Number 3115, 1997.

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