Michael Eisenring and Jurgen Teich, "Domain-specific interface generation from dataflow specifications", in Proc. of the 6 (CODES/CASHE'98), pp.43-47, 1998.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....primitives of the selected protocol is then inserted into the DesignUnits. The advantage with the method is its clean separation of communication from behaviour. A method arguing against the use of protocol libraries for selecting of an appropriate protocol is presented by Eisenring and Teich in [34, 35]. The multitude of different communication styles makes it inefficient to store all combinations of communication types in a library. Instead, they propose to store interfaces as classes in an object oriented library and having class methods describe how to generate the code for the interface. The ....

....in an object oriented library and having class methods describe how to generate the code for the interface. The approach has the advantage of producing code that is good for efficient implementation by the backend tool. A similar approach is presented by Vahid and Tauro in [33] In contrast with [34], they use classes of objects to encapsulate the code needed to describe the communication for different target implementations instead of generating it. Chou et al. present a set of techniques for performing hardware software interface synthesis [31] Software drivers and glue logic are ....

M. Eisenring, J. Teich, "Domain-Specific interface generation from dataflow specifications ", In Proc. of CODES 98, pp 43-47, Seattle Washington, March 15-18, 1998.

....The majority of the co design tools focus on the partitioning between hardware and software, and are used in the field of embedded systems [18] The system specifications can be implemented in hardware as in software. The specification is separated into a hardware part, a communication part [26, 25], and a software part. The software parts are translated to a programming language and implemented in the target platform. The hardware part is mapped to standard cells in ASIC design or Complex Logic Blocks (CLBs) in FPGA design. This is a fine grained structure in comparison to the large and ....

M. Eisenring and J. Teich. Domain-Specific Interface Generation From Dataflow Specifications. In Proc. of Codes/CASHE'98, the 6th Int. Workshop on Hardware/Software Codesign, pages 43--47, Seattle, Washington (USA), March 1998.

....on the channel. The library consists of a set of communication services and protocols along with their implementations (a mixture of hardware and software) Interface synthesis techniques are used to permit communication between the processor and the chosen communication units. Eisenring et al. [11] present a method for modelling the target architecture by means of object oriented methods. The architectural model is used to generate hardware software interfaces from data flow descriptions. LYCOS [16] COSYMA [12] and Vahid et al. 32] propose to solve the hardware software communication by ....

....a communication library. However, this only moves the problems of designing and maintaining device drivers from the designer to the provider of the library. The only approach that handles the mapping of hardware software communication on to DMA controllers is described by Eisenring and Teich [11], but their approach is limited to a set of standard APIs. Oberg et al. present a communication protocol synthesis tool that specifies the design in a special purpose language ProGram [34] which is based on context free grammar, the synthesizable subset is limited to regular grammar with ....

M. Eisenring and J. Teich, Domain-specific interface generation from dataflow specifications, Proceedings of the 6th International Workshop on Hardware/Software Codesign, pp. 43--47, 1998.

....to be able to reuse existing communication models through a library, to be able to choose between different communication protocols. 2. 2 Previous Work Most current approaches in communication synthesis for codesign have focused on interface synthesis for a homogeneous specification of systems [2,3,4,5]. In [6] Vahid presents an object oriented communication library for hardware software codesign. The PIA co simulation tool [7] allows to specify multiple communication models for each interface in the system and to switch dynamically to another communication model during the simulation run. The ....

Michael Eisenring and Jurgen Teich, "Domain-specific interface generation from dataflow specifications", in Proc. of the 6 th International Workshop on Hardware/Software Codesign (CODES/CASHE'98), pp.43-47, 1998.

....which integrates communication protocol selection with hardware software partitioning. The approach has been implemented as an extension to the LYCOS[6] cosynthesis system. Most current approaches to co synthesis consider communication synthesis to be a final step in the co synthesis trajectory [2][3][7] 8] For instance, 2] presents communication synthesis as an allocation problem to be solved after system level partitioning. However, as the level of communication overhead between system components influences what the best partition is, communication synthesis has to be integrated with ....

M. Eisenring and J. Teich. Domain-specific interface generation from dataflow specifications. In Proceedings of the 6th Codes/CASHE, pages 43--47, 1998.

....code to customize the device drivers and instantiate the kernel and user processes. 5.3 Other Approaches Communication and interface synthesis is an active area of research. Unfortunately, we are unable to cover all the approaches but refer the reader to the following further readings [23] [20] [27] 24] 37] 46] 6 Co Simulation and Co Verification Verification has traditionally been a very important aspect of interface design. In particular, given a set of partners, each one following its own protocol: 1. If the protocols are different (an interface must still be inserted) one ....

Michael Eisenring and Jurgen Teich. Domain-specific interface generation from dataflow specifications. In Proceedings of the Sixth International Workshop on Hardware/Software Codesign, pages 43--7, March 1998.

....FPGA reconfiguration while satisfying the given schedule. The result of this tool is a number of configurations per FPGA that contain all the necessary tasks and queues together with tasks responsible for reconfiguration control. The target object database provides object oriented target models [9] of the supported architecture components and currently contains models for XILINX FPGAs, a host PC, a DSP TMS320C6701 (TI) memories, and interfaces. The IP task queue database stores ## node implementations (cores) released for synthesis. Cores for FPGAs are described as synthesizable ....

....comprise computing resources and memories. There exist two types of computing resources: processors and FPGAs. Processors execute task nodes programmed in C. FPGAs implement task and buffer nodes programmed in VHDL or given as a netlist. The framework relies on an object oriented chip model [9] for the compoXILINX Xc4xxx MuxFF off chip FPGA computing resource chip model Direct on chip communication module architecture component concrete classes abstract classes consists of relation is a relation Figure 3: Part of the object oriented model of a XILINX FPGA. ....

[Article contains additional citation context not shown here]

EISENRING, M. and TEICH, J. DomainSpecific Interface Generation from Dataflow Specifications. In Sixth International Workshop on Hardware/Software Codesign, pages 43--47, Seattle, WA, March 1998.

....and edges of the task and architecture graph. As pointed out in section 1 the connection between heterogeneous system components is crucial for the overall design flow and therefore automatic interface generation is necessary. In this tool configuration (see Fig. 1b) CoFrame makes use of HASIS [7] [8] an object oriented toolset for automatic hardware software interface synthesis. Each computing resource of the architecture graph has an attribute TYPE referring to an object of the object database. Each of these objects models a real chip and possesses a core object representing the ....

....automatic hardware software interface synthesis. Each computing resource of the architecture graph has an attribute TYPE referring to an object of the object database. Each of these objects models a real chip and possesses a core object representing the computing engine and one or more IO objects [7] modeling the IO signaling facilities, e.g. bus interface, serial link, dedicated port, etc. The main feature of the IO objects are built in code generators able to generate various device drivers with different protocols for the IO modules of the real chip (see Fig. 4 for a general model of a ....

M. Eisenring and J. Teich. Domain-specific interface generation from dataflow specifications. In Proceedings of Sixth International Workshop on Hardware/Software Codesign, CODES 98, pages 43--47, Seattle, Washington, March 15-18 1998.

....one several tasks on different FPGAs X Y q Fig. 1. Taxonomy of communication types for the basic task queue task system 3. 1 On o# chip communication For on and o# chip communication, we leverage on our object oriented hardware software codesign tool for communication synthesis, HASIS [3] [4] HASIS copes with communication types 1, 2, 5 and 6 in Fig. 1. The key components of HASIS are configurable interface objects that generate dedicated VHDL interface code. HASIS maintains a set of object templates which can be easily extended by templates generated from scratch. As an ....

M. Eisenring and J. Teich. Domain-specific interface generation from dataflow specifications. In Proceedings of Sixth International Workshop on Hardware/Software Codesign, CODES 98, pages 43--47, Seattle, Washington, March 15-18 1998.

....FPGA reconfiguration while satisfying the given schedule. The result of this tool is a number of configurations per FPGA that contain all the necessary tasks and queues together with tasks responsible for reconfiguration control. The target object database provides object oriented target models [9] of the supported architecture components and currently contains models for XILINX FPGAs, a host PC, a DSP TMS320C6701 (TI) memories, and interfaces. The IP task queue database stores PG node implementations (cores) released for synthesis. Cores for FPGAs are described as synthesizable ....

....comprise computing resources and memories. There exist two types of computing resources: processors and FPGAs. Processors execute task nodes programmed in C. FPGAs implement task and buffer nodes programmed in VHDL or given as a netlist. The framework relies on an object oriented chip model [9] for the compo XILINX Xc4xxx MuxFF off chip FPGA computing resource chip model Direct on chip communication module architecture component concreteclasses abstractclasses consistsof relation isa relation Figure 3: Part of the object oriented model of a XILINX FPGA. ....

[Article contains additional citation context not shown here]

EISENRING, M. and TEICH, J. DomainSpecific Interface Generation from Dataflow Specifications. In Sixth International Workshop on Hardware/Software Codesign, pages 43--47, Seattle, WA, March 1998.

....and edges of the task and architecture graph. As pointed out in section 1 the connection between heterogeneous system components is crucial for the overall design flow and therefore automatic interface generation is necessary. In this tool configuration (see Fig. 1b) CoFrame makes use of HASIS [7] [8] an object oriented toolset for automatic hardware software interface synthesis. Each computing resource of the architecture graph has an attribute TYPE referring to an object of the object database. Each of these objects models a real chip and possesses a core object representing the ....

....automatic hardware software interface synthesis. Each computing resource of the architecture graph has an attribute TYPE referring to an object of the object database. Each of these objects models a real chip and possesses a core object representing the computing engine and one or more IO objects [7] modeling the IO signaling facilities, e.g. bus interface, serial link, dedicated port, etc. The main feature of the IO objects are built in code generators able to generate various device drivers with different protocols for the IO modules of the real chip (see Fig. 4 for a general model of a ....

M. Eisenring and J. Teich. Domain-specific interface generation from dataflow specifications. In Proceedings of Sixth International Workshop on Hardware/Software Codesign, CODES 98, pages 43--47, Seattle, Washington, March 15-18 1998.

....are partially repaired by a heuristic. For the same reason, bindings are not encoded directly by a bit vector, but rather indirectly by several lists. Intricate functions which depend on the allocation, binding, and scheduling are used to estimate the various objectives. The HASIS [7] synthesis system allows the generation of interfaces between hardware and software units, and supports a variety of processor families, communication channels and protocols. It provides a hybrid approach between library based interface instantiation [8] and synthesis from formal specifications ....

M. Eisenring and J. Teich, "Domain-Specific Interface Generation from Dataflow Specifications," in Proceedings of Sixth International Workshop on Hardware/Software Codesign, CODES 98, Seattle, Washington, March 15-18 1998, pp. 43--47.

....(ETH) Gloriastrasse 35, CH 8092 Zurich, Switzerland email: feisenring, teichg tik.ee.ethz.ch Abstract. The paper treats the problem of automatic generation of communication interfaces between hardware devices such as FPGAs and ASICs and software (programmable) devices such as microprocessors. In [2], we introduced an object oriented approach to interface generation starting from a coarse grain process graph specification level to the final device dependent implementation. Here, we present generic templates of how to implement hardware software interfaces, in particular in the scope of rapid ....

....of different design alternatives in the design space (rapid prototyping) has become a reachable goal. However, automatic interface synthesis, which generates a link between the communicating processes, becomes of increasing interest and importance and hence a key factor for rapid prototyping. In [2], we introduced an object oriented approach to automatic interface generation: Starting with a graphical specification in the form of a data flow graph (i.e. SDF graph [5] and given a partition of tasks (nodes) onto hardware and software modules, we explained how the required communication ....

[Article contains additional citation context not shown here]

M. Eisenring and J. Teich. Domain-specific interface generation from dataflow specifications. In Proceedings of Sixth International Workshop on Hardware/Software Codesign, CODES 98, pages 43--47, Seattle, Washington, March 15-18 1998.

No context found.

Michael Eisenring and Jurgen Teich, "Domain-specific interface generation from dataflow specifications", in Proc. of the 6 (CODES/CASHE'98), pp.43-47, 1998.

No context found.

Michael Eisenring and Jurgen Teich, "Domain-specific interface generation from dataflow specifications", in Proc. of the 6 International Workshop on Hardware/Software Codesign (CODES/CASHE'98), pp.43-47, 1998.

No context found.

M. Eisenring and J. Teich, "Domain-specific interface generation from dataflow specifications," in Proc. 6th Int. Workshop on Hardware /Software Codesign (CODES/CASHE'98), 1998, pp. 43--47.

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