S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli. Design of embedded systems: Formal models, validation, and synthesis. Proceedings of the IEEE, 85(3):366--390, March 1997.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....are only known by their outside interfaces, which may be defined at several levels as well. They are not tied to specific platforms. Their interfaces are flexible or ab stract, such that one or more layers of the protocol stack can be replaced without affecting the component functionality [8]. However, synthesis is required to map the abstract constructs to those in the concrete platform before the system is operational. Today s component models, whether platform based or interfacebased, commonly force designers to express coordination as an inseparable part of component ....

S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli. Design of embedded systems: Formal models, validation, and synthesis. Proceedings of the IEEE, 85(3):366--390, March 1997.

....agents in a formal logic framework. An essential aspect of the Metropolis methodology is the adoption of formal definition of the semantics of communication so that implementation choices will be correct by construction. Several formal models have been proposed over the years (see e.g. [6]) to capture one or more aspects of computation as needed in embedded system design. We have been able to compare the most important models of computations using a unifying theoretical framework introduced recently by Lee and Sangiovanni Vincentelli [5] However, this denotational framework has ....

S. Edwards, L. Lavagno, E. Lee, and A. SangiovanniVincentelli. Design of embedded systems: Formal models, validation, and synthesis. Proceedings of the IEEE, 85(3):366--390, Mar. 1997.

....It can be generalized that the main focus of all specification languages lies in managing system complexity. For this, they provide means to deal with concurrency and hierarchy as well as communication and synchronization mechanisms to organize data flow and timely inter dependencies [GVNG94, ELLSV97] Therefore, common to most languages are process models, whereas at this level of abstraction the term process denotes the concept of an autonomous object with its own thread of control. Synchronous languages like Esterel, Lustre, or Signal [Hal93] idealistically assume that processing of data ....

Stephen Edwards, Luciano Lavagno, Edward Lee, and Alberto SangiovanniVincentelli. Design of embedded systems: Formal models, validation, and synthesis. Proceedings of the IEEE, 85(3):366--390, mar 1997. Special Issue on Hardware/Software Co--Design. 9

....so that continuous signals are not seen by the discrete event simulator. Many MoCs have been devised and used. They differ because of characteristics such as ease of modeling, efficency of analysis (e.g. formal verification, simulation, etc. expressiveness, synthesizability, compositionality [12, 5]. Let us assume that the original specification be made up of continuous time components, discrete time components and X discrete event components, possibly intensively interacting with one another. We further assume, as discussed above, that the continuous components do not directly ....

S. Edwards, L. Lavagno, E.A. Lee, and A. SangiovanniVincentelli. Design of embedded systems: Formal models, validation, and synthesis. Proceedings of the IEEE, 85(3):366--390, March 1997.

....overview of the structure of the thesis. 1.1 Motivation 1.1.1 Embedded Systems Embedded systems play an increasingly important role in daily life. An embedded system can be defined as a system that uses a computer to perform a specific function, which is neither used nor perceived as a computer [27]. Embedded systems can be found in different application areas, such as train, car and aircraft controllers, consumer electronics, communication systems or medical devices. These embedded systems can include more and more functionality on a single chip due to Moore s law, which predicts that the ....

....synthesis process that allows the bridging of the abstraction gap in order to yield an efficient implementation. These objectives can be summarized as the challenge for a successful system design methodology. In order to manage the complexity and heterogeneity of SoC applications Edwards et al. [27] believe that the design approach should be based on the use of one or more formal methods to describe the behavior of the system at a high level of abstraction, before a decision on its decomposition into hardware and software is taken. The final implementation of the system should be made by ....

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S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli. Design of embedded systems: Formal models, validation, and synthesis. Proceedings of the IEEE, 85(3):366--390, March 1997.

....as a starting point for synthesis into hardware and software. In this paper we present the refinement process in our methodology. We discuss semantic preserving transformations and design decisions and illustrate them by the refinement of an equalizer system. 2. RELATED WORK Edwards et al. [5] use the tagged signal model, which is further elaborated by Lee and Sangiovanni Vincentelli in [8] to classify and analyze several models of computation, in particular discrete event models, communicating finite state machines, synchronous models and data flow process networks. It appears, that ....

S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli. Design of embedded systems: Formal models, validation, and synthesis. Proceedings of the IEEE, 85(3):366--390, March 1997.

....to post on servers or to redistribute to lists, requires prior specific permission and or a fee. DAC 2000, Los Angeles, California (c) 2000 ACM 1 58113 188 7 00 0006. 5. 00 stract, such that one or more layers of the protocol stack can be replaced without affecting the component functionality [8]. However, synthesis is required to map the abstract constructs to those in the concrete platform before the system is operational. Today s component models, whether platform based or interfacebased, commonly force designers to express coordination as an inseparable part of component ....

S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli. Design of embedded systems: Formal models, validation, and synthesis. Proceedings of the IEEE, 85(3):366--390, March 1997.

....plants, flight guidance of aircrafts and other strategic applications. All these applications require a computational system interacting with physicalequipments like sensors actuators that could even be electro mechanical systems. Such systems are often referred to as embedded systems [1, 6]. In other words, embedded systems are designed to perform a dedicated function rather than extensive computing. In a sense, in these systems hardware software are packaged together, perhaps along with electro mechanical or other types of systems. The ubiquitous concept of process control has lead ....

S. Edwards, L. Lavagno, E. Lee, and A. Sangiovanni-Vincentelli. Design of Embedded Systems: Formal Model, Validation, and Synthesis. In Proceedings of the IEEE, 85(3):366--390, March 1997.

....architecture. This state of the art methodology is an elegant two dimensional extention of the onedimensional High Level Synthesis (HLS) methodology [40] which has gained vast acceptance in both industry and academia [17, 68, 99] Three processes are identified in the embedded system design flow [32, 71]: 1. Modelling 2. Validation 3. Synthesis These processes are fundamental steps in any methodology aimed to design an embedded system. In addition, correctness identification and estimation are intermediate steps which might be part of the methodology. However, in most cases these steps are ....

Stephen Edwards, Luciano Lavagno, Edward Lee, and Alberto SangiovanniVincentelli. Design of embedded systems: Formal model, validation and synthesis. Proceedings of the IEEE, 85(3):366--390, March 1997.

....an MPEG 2 video decoder application. Keywords: platform based design, system level analysis, sto chastic automata networks, multimedia systems. 1. Introduction and objectives This paper presents a technique for system level power performance analysis that can be used in platform based design [1,2]. By plaOorm we mean a family of heterogeneous architectures that satisfy a set of architectural constraints imposed to allow re use of hardware and software components. While the technique that we propose is completely general and therefore can be used with any embedded application, we focus our ....

S. Edwards, L. Lavagno, E. A. Lee, A. Sangiovanni-Vincentelli, 'Design of embedded systems: formal models, validation, and synthesis,' Proc. IEEE, Vol.85, no.3, March, 1997.

....are used to describe hardware models, and software languages such as C, are used to describe embedded software code. The lack of a uniform specification increases the difficulty of the embedded system validation problem. Techniques for the formal validation of such systems are being developed [5]. Nevertheless, simulation is still the best option when trying to validate a design. As mentioned above, validation of embedded systems is hard because of their heterogeneity. Software and hardware should be simulated simultaneously, and furthermore hardware and software simulations must be kept ....

S. Edwards, L. Lavagno, E. Lee, , and A. Sangiovanni-Vincentelli. Design of Embedded Systems: Formal Models, Validation, and Synthesis. Proceedings of the IEEE, 85(3):336--390, 1997.

....functionality and timing [12] and signal reconstruction for increased visibility and reduced emulation bandwidth demands [13] A. Computation and Hardware Model Two main, often contradictory, criteria for evaluation of system and behavioral synthesis models of computations are expressiveness [6] and suitability for optimization. While high expressiveness implies wider application domain, suitability for optimization often implies efficient implementation. For the sake of conceptual simplicity, in this work, we target the 4 http: www.mentorg.com codesign main f index.htm. synchronous ....

S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli, Design of embedded systems: Formal models, validation, and synthesis, Proc. IEEE, vol. 85, pp. 366--390, Mar. 1997.

....handled by the Xtl model checker included in the Cadp toolbox. Keywords. Veri cation, Model Checking, LOTOS, Communicating Finite State Machine, Codesign. 1 Introduction For the design of complex systems the designers use ever more CAD tools working at the system level [GM93,Wol94,GV95,ELLSV97] Such tools o er generally the following capabilities : formal or abstract speci cation of the system, veri cation at the speci cation level, architecture exploration linked with performance analysis, automatic synthesis of behaviour and communication, automatic code generation, ....

S. Edwards, L. Lavagno, E.A. Lee, and A. Sangiovanni-Vincentelli. Design of Embedded Systems: Formal Models, Validation, and Synthesis. In Giovanni De Micheli, editor, Proceedings of the IEEE, Special issue on Hardware /Software Co-design, volume 85, pages 366-390. The institute of electrical and electronics engineers, inc., March 1997.

....main parameter, rather than its functionality. Heterogeneous models. Whenever differents views are needed (or it does not fit in all the above descriptions) Edwards et al. gives a good introduction to the design of embedded systems and shows that embedded systems are inherently heterogeneous [21]. Therefore, among the classification given 3 above, we found that the heterogeneous model is the most suitable for embedded system design representation. Most work in ESD is turning into this approach. We belive that a good ESD framework is not reached just by speeding up the algorithms involved ....

S. Edwards, L. Lavagno, E. Lee, and A. Sangiovanni-Vincentelli. Design of embedded systems: Formal model, validation and synthesis. Proceedings of the IEEE, 85(3):366--390, Mar. 1997.

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S. Edwards, L. Lavagno, E.A. Lee, and A. SangiovanniVincentelli. Design of embedded systems: formal models, validation, and synthesis. Proceedings of the IEEE, 85(3):366--390, March 1997.

....emphasize finite representations or executable models, which we defer for future work. 2. RELATED WORK In this section, we give a brief summary of the main approaches. We refer the reader to [6] for a more complete account of related work. Several formal models have been proposed over the years [9] to capture one or more aspects of computation in embedded systems. Many models of computation can be encoded in the Tagged Signal Model [10] In contrast, we describe a framework that is less restrictive in terms of what can be used to represent behaviors, and we concentrate on building ....

S. Edwards, L. Lavagno, E. Lee, and A. Sangiovanni-Vincentelli. Design of embedded systems: Formal models, validation, and synthesis. Proc. of the IEEE, 85(3):366--390, Mar. 1997.

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S. Edwards, L. Lavagno, E. Lee, and A. Sangiovanni-Vincentelli. Design of embedded systems: Formal models, validation, and synthesis. Proceedings of the IEEE, 85#3#:366#390, Mar. 1997.

....Later in the paper we consider examples of relationships that can we can build between some of the domains. These relationships are the basic tools to be used in studying the properties of heterogeneous systems. II. RELATED WORK Several formal models have been proposed over the years (see e.g. [12]) to capture one or more aspects of computation as needed in embedded system design. Many models of computation can be encoded in the Tagged Signal Model [16] However, because encoding is necessary, the level of abstraction is effectively changed, so some of the advantages of the original model ....

S. Edwards, L. Lavagno, E. Lee, and A. Sangiovanni-Vincentelli. Design of embedded systems: Formal models, validation, and synthesis. Proceedings of the IEEE, 85(3):366--390, Mar. 1997.

.... the environment under some timing constraints such as the speed (throughput) or the delay (latency) This work has been partially funded by CICYT 98 0410 and by a grant from Cadence Design Systems As embedded systems are highly concurrent by nature, specifications often employ formal models [6, 5] that expose parallelism explicitly. Some examples of formal models are data flow networks [15] Petri Net based models [7] Communicating Sequential Processes [13] and Kahn process networks [14] The implementation of these specifications is generally a software component running on top of a ....

S. Edwards, L. Lavagno, E. A. Lee, A. Sangiovanni-Vincentelli. Design of Embedded Systems: Formal Models, Validation, and Synthesis. In Proceedings of the IEEE, vol 85, NO. 3, 1997.

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S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-Vincentelli. Design of embedded systems: Formal models, validation, and synthesis. Proceedings of the IEEE, 85(3):366--390, March 1997.

No context found.

Stephen Edwards, Luciano Lavagno, Edward A. Lee, and Alberto Sangiovanni-Vincentelli. Design of embedded systems: Formal models, validation, and synthesis. Proceedings of the IEEE, 85(3):366--390, March 1997.

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S. Edwards, L. Lavagno, E.A. Lee, and A. Sangiovanni-Vincentelli. Design of embedded systems: Formal models, validation, and synthesis. In Proceedings of the IEEE, volume 85, pages 366--390, 1997.

No context found.

S. Edwards, L. Lavagno, E.A. Lee, A. SangiovanniVincentelli. Design of embedded systems: formal models, validation, and synthesis. Proceedings of IEEE, v.85, n.3, March 1997.

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S. Edwards, L. Lavagno, E.A. Lee, and A. Sangiovanni-Vincentelli. Design of Embedded Systems: Formal Models, Validation, and Synthesis. In Giovanni De Micheli, editor, Proceedings of the IEEE, Special issue on Hardware/Software Co-design, volume 85, pages 366--390. The institute of electrical and electronics engineers, inc., March 1997.

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Edwards, S., Lavagno, L., Lee, E., Sangiovanni-vincentelli, A. Design of Embedded Systems: Formal Models, Validation and Synthesis. Proceedings of the IEEE, 1997.

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