Chen, B.; Yamazaki, M.; Fujita, M.: Bug Identification of a Real Chip Design by Symbolic Model Checking; Proc. International Conference on Circuits And Systems (ISCAS'94), London, UK, June 1994, pp. 132-136.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....also compare our results to related work using HOL and VIS. In Section 9 we draw our conclusions. 2 Related Work There exist few results in the open literature that are directly related to the formal verification of ATM network hardware components. Chen et. al at Fujitsu Digital Technology Ltd. [5] exploited symbolic model checking to detect a design error in an ATM circuit. The ATM circuit consists of about 111K gates and supports highspeed switching operations at 156 MHz. When the circuit was manufactured it showed an abnormal behavior under certain circumstances. Using SMV (Symbolic ....

....state space explosion of even the most reduced model with a 4 bit datapath. Although Curzon [8] showed the effectiveness of HOL theorem proving for verifying an ATM switch, the use of HOL is interactive and requires much expertise to guide the verification process [14] The work at Fujitsu Ltd. [5] used the ROBDD based SMV model checker which is automatic and the authors succeed in checking some important properties related to the circuit implementation. Yet, the adopted data abstraction (e.g. using 1 bit to represent 8 bit data width) for avoiding state explosion is not always applicable. ....

B. Chen, M. Yamazaki, and M. Fujita, "Bug Identification of a Real Chip Design by Symbolic Model Checking," Proc. International Conference on Circuits And Systems (ISCAS'94), London, UK, pp. 132-136, June 1994.

....work using higherorder logic (HOL) and VIS. Finally, in Section IX, we draw some conclusions. II. RELATED WORK There exist few results in the open literature that are directly related to the formal verification of ATM network hardware components. Chen et al. at Fujitsu Digital Technology Ltd. [9] exploited symbolic model checking to detect a design error in an ATM circuit. The circuit consists of about 111 K gates and supports high speed switching operations at 156 MHz. When the circuit was manufactured it showed an abnormal behavior under certain circumstances. Using symbolic model ....

....While succeeding with model checking reduced models of the whole fabric and with equivalence checking of submodules of the design hierarchy, due to state space explosion, the VIS tool failed to complete the equivalence checking of even a very reduced model of the fabric. The work at Fujitsu Ltd. [9] used the ROBDD based SMV model checker and the authors succeeded in checking some important properties related to the circuit implementation. Yet, to avoid state explosion, the adopted data abstraction (e.g. using 1 bit to represent 8 bit data width) was not quite adequate, because it required ....

B. Chen, M. Yamazaki, and M. Fujita, "Bug identification of a real chip design by symbolic model checking," in Proc. Int. Conf. Circuits And Systems (ISCAS'94), London, U.K., June 1994, pp. 132--136.

....generated by random test pattern generators, or by hand. Simulation is simple, and scales well in the sense that the time taken to simulate is proportional to the design size. However, for large designs, the fraction of the state space which can be covered in this methodology is vanishingly small [1]. This state of affairs has led to the proposal of symbolic search strategies, based on the use of BDD s to implicitly represent set of states, next state functions, and perform basic FSM manipulations [4] Conceptually, these approaches systematically explore all states reachable from the ....

....the RTL code fragment shown in Figure 2. Here #, # and # are single assign a = input= 134) 1 : 0; always (posedge clk) begin if (a b) c=1; count = 2 b00; else if (c= 1) if (count= 2 b11) c=0; b=1; else count ; end Figure 2. RTL code fragment count[0] 1 count[1],1 a,1 c,1 b,1 Figure 3. Latch graph for code shown in Figure 2 bit latches and ##### is a 2 bit latch. Assume the target is ### ##. The initial latch graph will be as shown in Figure 3, assuming the initial values of all latches as #. For clarity, we do not show initial valued vertices in ....

B. Chen, M. Yamazaki, and M. Fujita. Bug Identification of a Real Chip Design by Symbolic Model Checking. In Proc. European Conf. on Design Automation, pages 132--136, March 1994.

....checking as a technique for hardware verification has been studied in academia at U.C. Berkeley using HSIS [Azi94] and at Carnegie Mellon University using SMV [McM93] Several case studies of formal verification in an industrial environment have been published in the past few years [Cla93] Lon93] [CYF94] [EM95] all of which used SMV as their model checker. These papers, in addition to demonstrating the use of model checking, offer some helpful suggestions and insights as to how to overcome size and expressibility problems. All of these case studies were done by formal verification experts, rather ....

B. Chen, M. Yamazaki and M. Fujita, "Bug identification of a Real Chip Design by Symbolic Model Checking", Proc. European Design and Test Conference, 1994, pp. 132-136.

....studies, with verification results. Discussions and conclusions are given in Section 5 and Section 6, respectively. 2. MODEL CHECKER AND LANGUAGE We used SMV [1] as our model checker because it has many good features to support real designs and there are many success stories from the industry [2][3] 4] 5] 6] 7] SMV supports various features to reduce the problem size, i.e. the scalarset data type for symmetric reduction, the ordset data type for induction, the subclass structure for case splitting, the layer structure for the compositional assume guarantee verification, and the property ....

B. Chen, M. Yamazaki, and M. Fujita, "Bug Identification of a Real Chip Design by Symbolic Model Checking," in ED&TC, pp. 132-136, 1994.

....algorithms that can directly operate on BDDs to formally verify properties, a process known as model checking. Model checking is the verification of properties, some of which may involve paths of the state graph and not just states, against the design. This is utilized with success in [Lon93] [CYF94] and [CGH 95] In model checking work with BDDs, temporal logic properties can also be checked. Temporal logic is a means to express properties which are true over a period of time. These temporal properties look for problems such as livelock (no forward progress) and process starvation (execution ....

Ben Chen, Masami Yamazaki and Masahiro Fujita, "Bug Identification of a Real Chip Design by Symbolic Model Checking", In Proceedings of the European Design Automation Conference, EDAC 1994.

....algorithm was presented in [VW86] In [CGH97] LTL model checking is performed using a tableau construction and running within SMV. Tableau construction for ACTL is presented in [GL94] In all these referenced works, the construction of the tableau is exponential in the length of the formula. In [CYF94] it is shown how to translate a specific CTL formula into an FSM in order to save run time, on the fly verification is not mentioned there and no other CTL formulas are discussed. Using regular expressions for specifications is discussed in [Wol81] for LTL) and in [IN97] for CTL) The rest of ....

B.Chen, M. Yamazaki, M. Fujita, "Bug Identification of a Real Chip Design by Symbolic Model Checking", Proc. European Design and Test Conference, 1994, pp. 132-136.

....generated by random test pattern generators, or by hand. Simulation is simple, and scales well in the sense that the time taken to simulate is proportional to the design size. However, for large designs, the fraction of the state space which can be covered in this methodology is vanishingly small [1]. This state of affairs has led to the proposal of symbolic search strategies, based on the use of BDD s to implicitly represent set of states, next state functions, and perform basic FSM manipulations [4] Conceptually, these approaches systematically explore all states reachable from the ....

....Some more edges can also be removed on basis of information from using Rule 1. For example, for the latch graph in Figure 3, we can remove edge from (b; 1) to (c; 1) After completing the above two steps, we will have two types of edges left in the latch graph. Some of these edges count[0] 1 count[1],1 a,1 c,1 b,1 Figure 3. Latch graph for code shown in Figure 2 are required condition edges found in first step; other edges correspond to those edges which did not get removed in universal quantification. Because of these edges the latch graph may not be a DAG. At this stage, we form the ....

B. Chen, M. Yamazaki, and M. Fujita. Bug Identification of a Real Chip Design by Symbolic Model Checking. In Proc. European Conf. on Design Automation, pages 132--136, March 1994.

....is simple, and scales well in the sense that the time taken to simulate is proportional to the design size. However, simulation offers no guarantee of correctness; more disturbingly, for large designs, the fraction of the design space which can be covered in this methodology is vanishingly small [3]. This state of affairs has led to the proposal of formal methods for design verification; the adjective formal refers to the unambiguous specification 1 of the system and the properties being checked, together with the validation step, which systematically explores all possible ways in which ....

B. Chen, M. Yamazaki, and M. Fujita. Bug Identification of a Real Chip Design by Symbolic Model Checking. In Proc. European Conf. on Design Automation, pages 132--136, March 1994.

....Decision Graphs) which proposes an automated decision graph approach of the switching element. Then, Paul Curzon and Sofi ene Tahar have compared their two different approaches in [49] Other people have investigated in the formal verification around the switching element. B. Chen and all [9] have verified an ATM circuit by Symbolic Model Checking ; K. Schneider and all [45] have validated the 4 by 4 switch using MEPHISTO, a verification system based on HOL. Tom Gebhardt at Oxford University have synthesized high level descriptions from formal specifications. Other works can be found ....

B. Chen, M. Yamazaki, and M. Fujita. Bug Identification of a Real Chip Design by Symbolic Model Checking. In Proc. of the Int. Conf. on Circuits and Systems, pages 132--136, June 1994.

....done by Curzon [3] using the HOL theorem prover. Tahar et al. 13] verified the same switch in an automatic fashion using the MDG (Multiway Decision Graphs) tools by property checking and equivalence checking. Lu et al. 10] also formally verified this same ATM switch fabric using VIS. Chen et al. [2] at Fujitsu Digital Technology, formally verified an ATM circuit using SMV. By using a combination of theorem proving and model 2 checking Rajan et al. 11] discovered bugs in a high level ATM model that was presumed correct during simulation. In this report, we investigate whether the formal ....

Chen, M. Yamazaki, and M. Fujita, "Bug Identification of a Real Chip Design by Symbolic Model Checking", Proc. International Conference on Circuits And Systems (ISCAS'94), London, U.K., pp. 132-136, June 1994.

....the ECL chip: a local area network interface which formed part of the Cambridge Fast Ring. This is of roughly similar complexity to the circuit we considered, though our HOL proof took less time, demonstrating the increased maturity of the system. B. Chen et. al at Fujitsu Digital Technology Ltd. [5] verified an ATM circuit that makes high speed switching operations at 156 MHz and consists of about 111K gates. When the circuit was manufactured it showed an abnormal behavior under certain circumstances. Using the SMV tool [22] the authors identified the design error by checking some ....

Chen, B., Yamazaki, M., and Fujita, M. 1994. Bug Identification of a Real Chip Design by Symbolic Model Checking. In Proceedings of International Conference on Circuits And Systems, London, UK, 132--136.

....generated by random test pattern generators, or by hand. Simulation is simple, and scales well in the sense that the time taken to simulate is proportional to the design size. However, for large designs, the fraction of the state space which can be covered in this methodology is vanishingly small [1]. This state of affairs has led to the proposal of symbolic search strategies, based on the use of BDD s to implicitly represent set of states, next state functions, and perform basic FSM manipulations [4] Conceptually, these approaches systematically explore all states reachable from the ....

....the RTL code fragment shown in Figure 2. Here a, b and c are single assign a = input= 134) 1 : 0; always (posedge clk) begin if (a b) c = 1; count = 2 b00; else if (c= 1) if (count= 2 b11) c = 0; b = 1; else count ; end Figure 2. RTL code fragment count[0] 1 count[1],1 a,1 c,1 b,1 Figure 3. Latch graph for code shown in Figure 2 bit latches and count is a 2 bit latch. Assume the target is (b; 1) The initial latch graph will be as shown in Figure 3, assuming the initial values of all latches as 0. For clarity, we do not show initial valued vertices in ....

B. Chen, M. Yamazaki, and M. Fujita. Bug Identification of a Real Chip Design by Symbolic Model Checking. In Proc. European Conf. on Design Automation, pages 132--136, March 1994.

....the ECL chip: a local area network interface which formed part of the Cambridge Fast Ring. This is of roughly similar complexity to the circuit we considered, though our HOL proof took less time, demonstrating the increased maturity of the system. Chen et al. at Fujitsu Digital Technology Ltd. [4] verified an ATM circuit that makes high speed switching operations at 156 MHz and consists of about 111K gates. When the circuit was manufactured it showed an abnormal behaviour under certain circumstances. Using the SMV tool [22] the authors identified the design error by checking some ....

B. Chen, M. Yamazaki and M. Fujita. Bug Identification of a Real Chip Design by Symbolic Model Checking. In Proceedings of the International Conference on Circuits and Systems, 132--136, 1994.

....for large designs, the fraction of the design space which can be covered in this methodology is vanishingly small. Indeed, there are many examples of designs that Supported by an NSF Career Award IWLS 1998 Submission 2 passed extensive simulation, but were still found to contain bugs [5]. This has led to the proposal of formal methods for design verification; the adjective formal refers to the unambiguous specification of the system and the properties being checked, together with the validation step, generating a mathematically rigorous proof of correctness. The computational ....

B. Chen, M. Yamazaki, and M. Fujita. Bug Identification of a Real Chip Design by Symbolic Model Checking. In Proc. European Conf. on Design Automation, pages 132--136, March 1994.

....is simple, and scales well in the sense that the time taken to simulate is proportional to the design size. However, simulation offers no guarantee of correctness; more disturbingly, for large designs, the fraction of the design space which can be covered in this methodology is vanishingly small [3]. This state of affairs has led to the proposal of formal methods for design verification; the adjective formal refers to the unambiguous specification of the system and the properties being checked, together with the validation step, which systematically explores all possible ways in which the ....

B. Chen, M. Yamazaki, and M. Fujita. Bug Identification of a Real Chip Design by Symbolic Model Checking. In Proc. European Conf. on Design Automation, pages 132-- 136, March 1994.

....design implicitly involves all cases of the input values. There exist only few references in the literature which address the formal verification of ATM related circuits. P. Curzon [3] formally verified the 4 by 4 fabric of the Fairisle switch fabric using the HOL theorem prover. B. Chen et al. [1] identified a design error in an ATM circuit using SMV (Symbolic Model Verifier) by verifying some properties expressed in CTL (Computational Tree Logic) ROBDD based verification requires a Binary representation of circuits. Recently, Multiway Decision Graphs (MDG) were proposed to represent ....

Chen, B. et al..: Bug Identification of a Real Chip Design by Symbolic Model Checking; Proc. International Conference on Circuits And Systems (ISCAS'94), London, UK, June 1994

....and scalability, simulation offers no guarantees of correctness; for large designs, the fraction of the design space which can be covered in this methodology becomes vanishingly small. Indeed, there are many examples of designs that passed extensive simulation, but were still found to contain bugs [4]. This has led to the proposal of formal methods for design verification; the adjective formal refers to the unambiguous specification of the system and the properties being checked, together with the validation step generating a mathematically rigorous proof of correctness. In theory the ....

B. Chen, M. Yamazaki, and M. Fujita. Bug Identification of a Real Chip Design by Symbolic Model Checking. In Proc. European Conf. on Design Automation, pages 132--136, March 1994.

....examining the output. This methodology offers no guarantees of correctness; for large designs, the fraction of the design which can be explored in this fashion becomes vanishingly small. There are many examples of designs that passed extensive simulation, but were still found to contain bugs [78, 54, 26]. Indeed verification is a major bottleneck in product development; in many cases the group performing verification is comparable in size to the design team itself. A formal methodology for verification consists of the following [4] 1. A set of rules to generate formulas describing systems, and ....

....then increases (because the clusters grow large) Summary In summary, it can safely be said that the use of symbolic methods has enabled the verification of a regime of designs that was previously impossible. Example of designs that were successfully verified using a BDD based approach include [19, 78, 26, 54]. These results underline the importance of an approach which can be easily used by designers. Since model checking can operate on descriptions similar to those which designers build for synthesis and simulation, it is gaining acceptance amongst designers. Additionally, there have been CHAPTER ....

B. Chen, M. Yamazaki, and M. Fujita. Bug Identification of a Real Chip Design by Symbolic Model Checking. In Proc. European Conf. on Design Automation, pages 132--136, March 1994.

.... In most cases the branching time logic CTL is used [ClEm81] since for this logic the model checking problem can be solved in linear time with regard to the size of the formula and the model [Emer90] This technique has been already successfully applied to the verification of real word examples [CGHJ93a, ChYF94]. However, since a finite state model of the system is required, the state explosion problem occurs: the number of states may grow exponentially with the number of storage elements of a circuit and thus even for medium sized examples the state space becomes infeasible. To reduce the verification ....

B. Chen, M. Yamazaki, and M. Fujita. Bug identification of a real chip design by symbolic model checking. In Proc. European Design and Test Conference, pages 132--136. IEEE Computer Society Press, February 1994.

....and scalability, simulation offers no guarantees of correctness; for large designs, the fraction of the design space which can be covered in this methodology is vanishingly small. Indeed, there are many examples of designs that passed extensive simulation, but were still found to contain bugs [5]. This has led to the proposal of formal methods for design verification. The computational complexity of invariant checking on netlists is very high. In practice, many designs are well structured, and this can be exploited to devise heuristic procedures that perform well on specific classes of ....

B. Chen, M. Yamazaki, and M. Fujita. Bug Identification of a Real Chip Design by Symbolic Model Checking. In Proc. European Conf. on Design Automation, pages 132--136, March 1994.

....efforts is that with any change of switch design requirements such as the clock ratio and the number of input output ports, one needs to repeatedly iterate through high level modeling, validation, and synthesis cycle until the design satisfies the design objectives. Furthermore, earlier efforts [CYF94, TZS 96, Cur94] do not introduce formal validation early in the design cycle, rather describe application of formal verification on a completed design post facto. In order to cut down the modeling validation synthesis iteration cycle, the solution we propose in this paper is the development ....

....by simulation, we obtain the following overall correctness property: Theorem 3.5 (ATM Switch Correctness) Every input cell is switched to the proper output port, and the order among the cells at an output port is identical to that at the corresponding input port. 4 Summary In earlier work [CYF94] a number of abstractions had to be manually applied without any computeraided tool applied to formally verify an industrial ATM switch design using SMV based model checking [McM93] The verification successfully revealed the bugs and the design was corrected. But, such a post facto verification ....

B. Chen, M. Yamazaki, and M. Fujita. Bug identification of a real chip design by symbolic model checking. In Proceedings of the European Conference on Design Automation, the European Test Conference, pages 132--136, Paris, France, February 1994. IEEE Computer Society.

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Chen, B.; Yamazaki, M.; Fujita, M.: Bug Identification of a Real Chip Design by Symbolic Model Checking; Proc. International Conference on Circuits And Systems (ISCAS'94), London, UK, June 1994, pp. 132-136.

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Chen, B.; Yamazaki, M.; Fujita, M.: Bug Identification of a Real Chip Design by Symbolic Model Checking; Proc. International Conference on Circuits And Systems (ISCAS'94), London, UK, June 1994, pp. 132-136.

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Chen, B.; Yamazaki, M.; Fujita, M.: Bug Identification of a Real Chip Design by Symbolic Model Checking; Proc. International Conference on Circuits And Systems (ISCAS'94), London, UK, June 1994, pp. 132-136.

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