QUACH, N., AND FLYNN, M. Design and implementation of the SNAP floating-point adder. Tech. Rep. CSL-TR-91-501, Stanford University, December 1991.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....comparison with other floating point addition algorithms. 1 Introduction Floating point addition and subtraction are the most frequent floating point operations. Both operations use a floating point (FP) adder. Therefore, a lot of effort has been spent on reducing the latency of FP adders (see [7, 14, 13, 12, 11] and the references that appear there) Data about the latency of manufactured FP adders is often given in technology dependent terms (e.g. measured latency in nano seconds) and one can learn very little about the algorithms employed and their latency in technology independent terms. This brings ....

Nhon Quach and Michael Flynn. Design and implementation of the snap floating-point adder. Technical Report CSL-TR-91-501, Stanford University, Dec. 1991.

....based on the sequence of significand operations: swap, shift, add, normalise and round. They also discuss how to construct faster FP adders. Implementations of FP adders are reported in [6, 7, 12, 5, 9, 13, 10] Algorithms and circuits which have been used to improve their design are described in [17, 8, 3, 20, 16, 21, 15, 22, 19]. Some of these improvements are as follows: ffl the serial computations such as additions can be reduced by placing extra adders (or parts thereof) in parallel to compute speculative results for exponent subtraction (E a Gamma E b and E b Gamma E a ) and rounding (M a M b and M a M b 1) ....

....phases are disjoint operations for large shifts. However there is a significant increase in hardware cost since the significand addition hardware cannot be shared as with the traditional three stage pipeline. Other FP adder designs have moved the rounding stage before the normalisation [21, 19, 12]. Quach and Flynn describe an FP adder [21] which uses a compound significand adder with two outputs plus a row of half adders and effectively has a duplicated carry chain. Kowaleski et al. 12] describe an adder as part of a 263,000 transistor FP unit which contains separate add and multiply ....

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N. Quach and M. Flynn. Design and implementation of the snap floating-point adder. Technical Report CSL-TR91 -501, Stanford University, Dec. 1991.

....carries are used to select among the two sums. On the other hand, there are several applications that require the computation of the sum and the sum plus 1. For example, rounding in floating point addition is made faster by merging the significand addition and rounding steps with a dual adder [9, 10]. This adder computes simultaneously A B and A B 1, being A and B the aligned significands. Depending on rounding bits and the most significant bits of A B, A B or A B 1 is selected as the rounded result and then it is normalized. This way, the normalization of the result is performed ....

N.T. Quach and M.J. Flynn. Design and Implementation of the SNAP Floating Point Adder. Technical Report CSL--TR--91--501. Stanford University. (1991). 29

....after the rounding. However, in this approach, the selection between A B and A B 1 depends on the most significant 1 bits of the result, in addition to the guard bits. If these most significant bits are obtained from the result of the addition, the selection adds an appreciable delay [9]. On the other hand, these bits can be obtained from the carry into the most significant bit, so that an early determination of this carry reduces the overall delay. Another example is the last step in division and square root by digit recurrence [1] where the quotient has to be decremented by ....

N.T. Quach and M.J. Flynn. Design and Implementation of the SNAP Floating Point Adder. Technical Report CSL--TR--91--501. Stanford University. (1991).

....upon the realization that the rounding step occurs very late in the computation, and it only modifies the result by a small amount. By precomputing all possible required results in advance, rounding and conversion can be reduced to the selection of the correct result, as described by Quach [33] [34]. Specifically, for the IEEE round to nearest (RN) rounding mode, the computation of A B and A B 1 is sufficient to account for all possible rounding and conversion possibilities. Incorporating this optimization into Two Path requires that each significand adder compute both sum and sum 1, ....

N. Quach and M. Flynn, "Design and implementation of the SNAP floating-point adder," Technical Report No. CSL-TR-91-501, Computer Systems Laboratory, Stanford University, December 1991.

....(FP to integer conversion) 12] in Intel s Pentium Pro and Pentium II processors have demonstrated the importance and the difficulty of verifying FP arithmetic circuits and the high cost of an arithmetic bug. FP adders are the most common units in FP processors. Modern high speed FP adders [17] are very complicated, because they require many types of modules: a right shifter for alignment, a left shifter for normalization, a leading zero anticipator (LZA) an adder for mantissas, and a rounding unit. Formal verification or exhaustive simulation can be used to ensure the correctness of ....

....short circuiting technique can be used when different parts of the circuit are used under different operating conditions. We used our system and these specifications to verify the FP adder in the Aurora III Chip [14] at the University of Michigan. This FP adder is based on the design described in [17], and supports IEEE double precision and all 4 IEEE rounding modes. In this verification work, we verified the FP adder only in the round to nearest mode, because we believe that this is the most challenging rounding mode for verification. Our system found several design errors. Each specification ....

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QUACH, N., AND FLYNN, M. Design and implementation of the SNAP floating-point adder. Tech. Rep. CSL-TR-91-501, Stanford University, December 1991. This article was processed using the L A T E X macro package with LLNCS style

....path. This encoding is needed to perform the normalization of the result. Since the latency of floating point addition is significant in many applications, this prediction might be of practical importance and is incorporated in several floating point unit designs and commercial processors 1 [2, 3, 4, 5, 6, 9, 10]. We develop here an enhancement of the LOP to reduce the latency even further. The encoding of the position of the leading one is necessary when the difference between the exponents of the two operands is zero or one and the effective operation of the adder is a subtraction. In this case, the ....

N.T. Quach and M.J. Flynn. Design and Implementation of the SNAP Floating Point Adder. Technical Report CSL--TR--91--501. Stanford University. (1991.)

....chip area and the latter tends to degrade the performance. Furthermore, in both cases renormalization might occur due to an overflow from the rounding operation. In this research, a FPASR which performs rounding and addition subtraction in parallel is proposed and algebraically analyzed. In [2] [9], rounding and addition subtraction can be performed in parallel. But in [9] the FPASOP is executed into two paths depending on the absolute difference of the exponents. Then, because controlling the two dataflows is much more complex than the conventional one, it requires additional complex ....

....both cases renormalization might occur due to an overflow from the rounding operation. In this research, a FPASR which performs rounding and addition subtraction in parallel is proposed and algebraically analyzed. In [2] 9] rounding and addition subtraction can be performed in parallel. But in [9], the FPASOP is executed into two paths depending on the absolute difference of the exponents. Then, because controlling the two dataflows is much more complex than the conventional one, it requires additional complex logics and complex routings to be difficult to implement. Therefore, it causes ....

[Article contains additional citation context not shown here]

Nhon Quach and Micheal J. Flynn, "Design and implementation of the SNAP floating-point adder," CSL-TR-91-501, Stanford University, Dec. 1991.

....conversion) 14] in Intel s Pentium Pro and Pentium II processors have demonstrated the importance and the difficulty of verifying floating point arithmetic circuits and the high cost of an arithmetic bug. FP adders are the most common units in floating point processors. Modern highspeed FP adders [20, 23] are very complicated, because they require many types of modules: a right shifter for alignment, a left shifter for normalization, a leading zero anticipator (LZA) an adder for mantissas, a rounding unit, etc. Exhaustive simulation or formal verification can be used to ensure the correctness of ....

....short circuiting technique can be used when different parts of the circuit are used under different operating conditions. We used our system and these specifications to verify the FP adder in the Aurora III Chip [16] at the University of Michigan. This FP adder is based on the design described in [20], and supports IEEE double precision and all 4 IEEE rounding modes. In this verification work, we verified the FP adder only in the round to nearest mode, because we believe that this is the most challenging rounding mode for verification. Our system found several design errors. Each specification ....

[Article contains additional citation context not shown here]

QUACH, N., AND FLYNN, M. Design and implementation of the SNAP floating-point adder. Tech. Rep. CSL-TR-91-501, Stanford University, December 1991.

....the amount of the shift for normalization from the operands. Once the result of the addition is obtained, the normalization shift can be performed since the shift has been already determined. This approach has been used in some recent floating point unit design and commercial processors [3, 7, 8, 9, 11, 18, 19]. As described below, the basic schemes developed for the leading one predictor give the position with a possible error of one bit. Because of this, a second step consists of detecting and correcting this error, but this step increases the overall delay. To avoid this delay increase, we propose a ....

N.T. Quach and M.J. Flynn. Design and Implementation of the SNAP Floating Point Adder. Technical Report CSL--TR--91--501. Stanford University. (1991.)

....based upon the realization that the rounding step occurs very late in the computation, and it only modifies the result by a small amount. By precomputing all possible required results in advance, rounding and conversion can be reduced to the selection of the correct result, as described by Quach [11, 12]. Specifically, for the IEEE round to nearest (RN) rounding mode, the computation of A B and A B 1 is sufficient to account for all possible rounding and conversion possibilities. Incorporating this optimization into Two Path requires that each significand adder compute both sum and sum 1, ....

N. Quach and M. Flynn. Design and implementation of the SNAP floating-point adder. Technical Report No. CSL-TR-91-501, Computer Systems Laboratory, Stanford University, December 1991.

....based upon the realization that the rounding step occurs very late in the computation, and it only modifies the result by a small amount. By precomputing all possible required results in advance, rounding and conversion can be reduced to the selection of the correct result, as described by Quach [8, 9]. Specifically, for the IEEE round to nearest (RN) rounding mode, the computation of A B and A B 1 is sufficient to account for all possible rounding and conversion possibilities. Incorporating this optimization into Two Path requires that each significand adder compute both sum and sum 1, ....

N. Quach and M. Flynn. Design and implementation of the SNAP floating-point adder. Technical Report No. CSL-TR-91-501, Computer Systems Laboratory, Stanford University, December 1991.

....FADD algorithm that minimizes these addition steps, thus offering a considerable speed advantage over the earlier ones. Section 2 reviews the existing algorithms and traces their evolution. Section 3 presents the main ideas behind the proposed algorithm. The reader is referred to Quach and Flynn [37, 38] for a detailed derivation of the equations. Section 4 describes the implementation of a test chip. Concluding remarks are given in Section 5. In this chapter, A = a 0 a 1 . a n Gamma1 denotes an n bit vector or an n bit operand. The A term denotes the bit inversion of A. The Q:y term denotes ....

....of the total area with the rest of the area consumed by wires and dead spaces. CHAPTER 4. HIGH SPEED FP ADDITION 45 4.4.3 Methodology Before the implementation, all the logic equations are derived and simulated on a simulator written in the C language. The reader is referred to Quach and Flynn [37, 38] for a discussion on the derivation of the logic equations. The simulator simulates both the algorithm and the logic optimization. Both single precision and double precision operations are simulated. Half a billion randomly generated vectors were tested. In parallel, the basic building blocks ....

N. T. Quach and M. J. Flynn, "Design and Implementation of the SNAP Floating-Point Adder," Tech. Rep. CSL-TR-91-501, Stanford University, Dec 1991. BIBLIOGRAPHY 87

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QUACH, N., AND FLYNN, M. Design and implementation of the SNAP floating-point adder. Tech. Rep. CSL-TR-91-501, Stanford University, December 1991.

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