S.F. Oberman and M.J. Flynn. A variable Latency Pipelined Floating--point Adder. Technical Report CSL--TR--96--689. Stanford University. (1996).  Home/Search   Document Details and Download   Summary   Related Articles   Check

....and, therefore, if the addition is performed in one s or two s complement format, it is necessary to convert the significand result, when negative, to a sign magnitude representation. This conversion is carried out before the normalization. To reduce the overall operation delay or latency, in [8, 9] it has been proposed to use a compound adder that computes simultaneously A B and A B 1. This permits, taking advantage of mutually exclusive steps, to merge the significand addition and rounding steps. Thus, the result normalization can be carried out after the rounding, since rounding and ....

....the rounding adder operate in parallel, since the full normalization shift, which occurs only in an effective subtraction with exponent difference d = 0; 1, and the rounding are mutually exclusive steps. Finally, figure 1c) shows an architecture which implements the datapath as a double datapath [8, 9]: the CLOSE datapath, which computes the effective subtractions for an exponent difference zero or one, and the FAR datapath, where all the effective additions and the effective subtractions for an exponent difference larger than 1 are computed. This architecture exploits several aspects of the ....

S.F. Oberman and M.J. Flynn. A variable Latency Pipelined Floating--point Adder. Technical Report CSL--TR--96--689. Stanford University. (1996).

....no data are lost. Of course, the results should be provided as fast as possible. So far, the local scheduling problem has been solved for simple designs, e.g. by stalling in case of a long latency instruction. More elaborate variable latency FUs are just emerging now, like the multi path adder of [38] or the self timed division units [46, 5] For those designs, the local scheduling has not been addressed yet. C12, C13] therefore present a dynamic scheduler which can govern the data flow within any variable latency FU, whose structure can be represented by a directed acyclic graph with a ....

S.F. Oberman and M.J. Flynn. A variable latency pipelined floating-point adder. In Proc. EUROPAR'96 Parallel Processing, volume LNCS 1124, pages 183--192. Springer, 1996.

....be provided as fast as possible. So far, the local scheduling problem has been solved for simple designs, e.g. by stalling in case of a long latency instruction. More elaborate variable latency FUs research performed during a stay at MIT Laboratory for Computer Science are just emerging now [6], but for those designs, the local scheduling has not been addressed yet. This paper presents a dynamic scheduler which can govern the data flow within any variable latency FU, as long as the structure of the FU can be represented by a directed acyclic graph with a single source and sink. The FU ....

....However, with a little extra hardware, they can be processed in parallel to the regular computation. That simplifies the FU data paths and allows for a faster cycle time. ffl There is also a big potential in exploiting the characteristics of an operation, as it is done in the multipath adder [6]. Depending on the distance of the operands and their signs, such an adder performs the actual addition in one, two or three cycles. These four concepts can, of course, be combined. Figure 1 illustrates the structure of such an adder. Its latency unpack denormal input slow add 1 fast add 1 ....

[Article contains additional citation context not shown here]

S.F. Oberman and M.J. Flynn. A variable latency pipelined floating-point adder. In Proc. EUROPAR'96 Parallel Processing, volume LNCS 1124, pages 183--192. Springer, 1996.

....no data are lost. Of course, the results should be provided as fast as possible. So far, the local scheduling problem has been solved for simple designs, e.g. by stalling in case of a long latency instruction. More elaborate variable latency FUs are just emerging now, like the multi path adder of [OF96] or the self timed division units [SL97, CL93] For those designs, the local scheduling has not been addressed yet. Contribution This paper therefore presents a dynamic scheduler which can govern the data flow within any variable latency FU, as long as the structure of the FU can be represented by ....

.... fast add 1 fast add 2 slow add 2 slow add 3 pack denormal, exception 3 path adder Figure 1: Structure of a variable latency floating point adder using a 3 path adder core ffl There is also a big potential in exploiting the characteristics of an operation, as it is done in the multi path adder [OF96]. Depending on the distance of the operands and their signs, such an adder performs the actual addition in one, two or three cycles. These four aspects can, of course, be combined. Figure 1 illustrates the structure of such an adder. Its latency varies between two and seven cycles; that includes ....

[Article contains additional citation context not shown here]

S.F. Oberman and M.J. Flynn. A variable latency pipelined floating-point adder. In Proc. EUROPAR'96 Parallel Processing, volume LNCS 1124, pages 183--192. Springer, 1996.

....COMPOUND ADDER EXPONENT SUBTRACT alignment 1 bit shift EXP. INCR. control mux OUTPUT ALIGNER EXP. INCR. shift Compensate Figure 15: Latency of the double datapath floating point adder Latency reduction in double datapath floating point adders Figure 15 shows an double datapath architecture [11, 12]. In it, the FAR datapath computes effective subtractions with exponent differences larger than one as well as all effective additions. On the other hand, effective subtractions with an exponent difference equal or smaller than one are computed in the CLOSE datapath. The pipelining of the adder ....

S.F. Oberman and M.J. Flynn. A variable Latency Pipelined Floating--point Adder. Technical Report CSL--TR--96--689. Stanford University. (1996).

....in high clock rate microprocessors has been three cycles, with a throughput of one cycle. To further reduce the latency, we observe that not all of the components are needed for all input operands. Two VLA techniques are proposed to take advantage of this to reduce the average addition latency [23]. To effectively use average latency, the processor must be able to exploit a variable latency functional unit. The processor might use some form of dynamic instruction scheduling with out of order execution in order to use the reduced latency and achieve maximum system performance. 25 CHAPTER ....

S. F. Oberman and M. J. Flynn, "A variable latency pipelined floating-point adder," in Proceedings of Euro-Par'96, Springer LNCS vol. 1124, August 1996, pp. 183--192.

....of these is sufficient to give the final correct result of a floating point addition. Control circuitry to select which of the possible precomputed outcomes is the correct one. It is possible to take this one step further, using variable latency algorithms which are recently developed by Oberman [7]. This approach recognizes that there are many common cases where the result could be available early. For example, in certain cases, the two operands have the same exponent (the CLOSE case) and the operation is addition, so only the simple left shift could be required. In another case, if the ....

S. F. Oberman and M. J. Flynn, "A variable latency pipelined floating-point adder." In Proc. Euro-Par'96, Springer LNCS, pp. 183--192, Aug. 1996.

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