Weems, C. "Considerations Leading to an Asynchronous SIMD Architectural Approach for Exploiting Mixed Logic and Memory," Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, Denver, CO, USA, 1 June 1997. (http://iram.cs.berkeley.edu/isca97-workshop/w2-108.ps)  Home/Search   Document Not in Database   Summary   Related Articles

....Putting a conventional cache based, superscalar microprocessor in an IRAM does not lead to exciting performance. 7] 14] Hence IRAM needs a new architecture. If an architecture requires programmers to rewrite their programs, then it needs advantages of factors of at least 10 and as much as 50. [15] The reason for this high threshold is that software development is slow, and with conventional microprocessor performance doubling every 18 months, there must still be a large advantage after the programming is completed. Otherwise programmers will just wait, as in the long run novel machines are ....

Weems, C. "Considerations Leading to an Asynchronous SIMD Architectural Approach for Exploiting Mixed Logic and Memory," Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, Denver, CO, USA, 1 June 1997. (http://iram.cs.berkeley.edu/isca97-workshop/w2-108.ps)

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC