Cray Research, Inc., "CRAY-I Compmer Systems, Hardware Reference Manual,' Chippewa Falls. WI, 1979, Home/Search Document Not in Database Summary Related Articles Check |
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Implementation Of Precise Interrupts In Pipelined Processors - James Smith Departmvnt (1985) (52 citations) (Correct)
....through the pipeline in order with a stage at the end where exCCPnon conditions are checked before the process stae is modified. Examples include the Amdahl 470 and 5g0 [Amdhgl.Amdhg0] and the Gould SEl. 32 g7 [Aardg2] The high performance CDC 6600 [Thor70] CDC 7600 [Buns69] and Cray Research [Russ7g, Cray79] computers allow insu uctions to complete out of Ihe architectural sequence. Consequently, they. have some exption conditions that result in imprecise interrupts. In these machines. the advantages of precise interrupts have been sacrificed in favor of maximum parallelism and design simplici . I O ....
Cray Research, Inc., "CRAY-I Compmer Systems, Hardware Reference Manual,' Chippewa Falls. WI, 1979,
An Instruction Set and Microarchitecture for Instruction Level.. - Kim, Smith (2002) (13 citations) (Correct)
.... is not needed (statistics are given in Section 4) Having the memory address available at issue time has other advantages; for example, store address queue checking can be done as part of the issue function, in much the same way as the Cray 1 does memory bank conflict checking at issue time [7]. Block I Cache Parcel GPR Rename Steer PE 7 PE 6 . L2 Cache P a) Block diagram of ILDP processor U X ALU L1 Cache from Register ICN to Reg ister ICN L1 replication network to L2 cache B U X M U X Ins t. F IFO GPRs IR control b) Processing element (ICN stands ....
CRAY-1 S Series, Hardware Reference Manual, Cray Research, Inc., Publication HR-808, Chippewa Falls, WI, 1980.
Strategies for Achieving Improved Processor Throughput - Matthew Farrens (1991) (14 citations) (Correct)
....traces were generated for each of the benchmark programs and then used to drive the simulations. No modifications to the code were performed; the code used is that produced by the Cray Fortran Compiler. The simulator uses a processor model that is a slight variant of the CRAY 1S processor [CRAY82,Russ78]. # # The hardware functional units in the simulator have the same performance characteristics as the CRAY 1 functional units; the time taken for a scalar add is 2 clock cycles, floating point multiply take 7 clock cycles, etc. The register files are also configured as in the CRAY 1. The only ....
CRAY-1 Computers, Hardware Reference Manual, Chippewa Falls, WI, Cray Research Inc., 1982.
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