S. Dickey, et al., "A VLSI Combining Network for the NYU Ultracomputer," in Proc. Int'l Conf. Computer Design, pp. 110- 113, Oct. 1985.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....known. However, for any arbitrary application, it may not be easy to identify hotspot locations. In the hardware approach, extra hardware is employed either to control the hotspot traffic by reducing the effects of the tree saturation [6] 2] 16] 7] or to remove the tree saturation completely [12][4][5] 1] 9] 10] 13] One of the hardware approaches is the combining network proposed in the NYU Ultracomputer [4] 5] In this approach, a class of combinable hotspot packets are defined. A hotspot traffic combining logic is deployed in each outpout queue of a switch element. Two hotspot packets ....

.... approach, extra hardware is employed either to control the hotspot traffic by reducing the effects of the tree saturation [6] 2] 16] 7] or to remove the tree saturation completely [12] 4] 5] 1] 9] 10] 13] One of the hardware approaches is the combining network proposed in the NYU Ultracomputer [4][5] In this approach, a class of combinable hotspot packets are defined. A hotspot traffic combining logic is deployed in each outpout queue of a switch element. Two hotspot packets can be combined into a single hotspot packet in an output queue as long as they are heading towards the same ....

[Article contains additional citation context not shown here]

S. Dickey, et al., "A VLSI Combining Network for the NYU Ultracomputer," in Proc. Int'l Conf. Computer Design, pp. 110- 113, Oct. 1985.

....among competing asynchronous agents. Any environment that admits asynchronous independent agents must regulate competition for shared resources. In the world of multiprocessors, perhaps the most visible instance of such competition involves concurrent memory access in shared memory architectures [2, 10]; the cited sources use combining networks to solve this problem. In the world of uniprocessors, one encounters essentially the identical problem in several scenarios, including the regulation of direct memory access (DMA) devices [12] in this case, the smaller number of competitors allows one ....

S. Dickey, R. Kenner, M. Snir, J. Solworth (1985): A VLSI combining network for the NYU Ultracomputer. NYU Ultracomputer Note No. 85.

....and RP3. It presents a general formulation of RMW operations and of combining for these operations. On the other hand, we have not discussed implementations of the combining logic. An implementation of an efficient switch that supports combining of fetch and add requests is described in [DKS] [DKSS]. This design has been realized in custom VLSI at NYU. The same scheme can be used for other RMW operations. This realization, while reasonably fast, requires significant amounts of supplementary hardware (over that required for packet switching) Note that one can use combining logic that detects ....

Dickey, S., R. Kenner, M. Snir, and J. Solworth, A VLSI Combining Network for the NYU Ultracomputer, IEEE Proc. of the Intl. Conf. on Computer Design, pp. 110-113, Oct. 1985.

....queues, which are simpler to design and need fewer hardware resources per queue item than the two input queues required in the Type A design. Type B has four of these simpler queues, one for each input output pair, and is the one that has been used to implement the NYU Ultracomputer switching node [3, 5]. Type C has only two queues, one at each input, and is very attractive to hardware designers because of its simplicity. However, the bandwidth of the Type C switch is limited due to blocking when both queues have a message for the same output. This bandwidth limitation was demonstrated in ....

....controls which output from the switch will be taken [1] The analysis of 2 2 switches in this paper thus assumes that the output by which a message must leave a switch is fixed before it enters the switch. A systolic queue design is used in the NYU Ultracomputer s 2 2 buffered switching components [3]. This is a synchronous design, making the continuous time arrival assumptions of classical queueing theory inappropriate. Our analysis makes a direct but nontrivial extension of queueing theory to networks with quantized time. Throughout the analysis we make use of generating functions. Readers ....

Dickey, S., Kenner, R., Snir, M. and Solworth, J. A VLSI Combining Network for the NYU Ultracomputer. Proceedings of the International Conference on Computer Design. October 7, 1985, pp. 110 - 113.

....queue can be replaced with four one input queues. Depending on the protocol used, the queues fed by the wait buffers may only require space for one message. Details of the current switch design and a description of an implementation for a planned 32 PE prototype can be found in Dickey et al. [2, 3] and Gottlieb [7] 3.4. Combining and its implementation cost Our design for combining and non combining queues is an enhancement of the VLSI systolic queue of Guibas and Liang [11] They present a FIFO buffer where an insertion or deletion can be performed every four cycles, and where no global ....

S. Dickey, R. Kenner, M. Snir, and J. Solworth, "A VLSI Combining Network for the NYU Ultracomputer", Proc. Intern. Conf. on Comp. Design, 1985.

....kinds of operations which can be combined. 2.2.1. Combining messages Combining messages when they meet at a switch is one example of such increased functionality. In particular, the Ultracomputer project has proposed combining fetch and add operations as well as loads and stores at the switches [1] [5] The fetch and add operation, useful as a synchronization primitive and in many parallel algorithms, is an indivisible add to memory; its format is F A(X,e) where X is an integer variable and e is an integer expression. The operation is defined to return the (old) value of X and to replace X ....

S. Dickey, R. Kenner, M. Snir and J. Solworth, "A VLSI Combining Network for the NYU Ultracomputer," Proceedings of the International Conference on Computer Design, pp. 110 - 113, October 7, 1985.

....to follow, switches and networks refer to the forward direction except where the return network is explicitly mentioned. In this study, we restrict the switch nodes to a class that supports a specific communication protocol, the Ultraswitch protocol, developed by the NYU Ultracomputer project [10, 31]. By omitting some implementation specific features, our description of the protocol is somewhat more general than the actual Ultracomputer hardware implementation. In the Ultraswitch protocol, we assume that networks are n = log k N stage Omega networks constructed from k k switches. There are ....

Susan R. Dickey, Richard Kenner, Marc Snir, and Jon Solworth, "A VLSI Combining Network for the NYU Ultracomputer", Proc. International Conference on Computer Design, pp. 110-113 (1985).

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC