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E. M. Sentovich et. al., "SIS: A system for sequential circuit synthesis," in Department of Electrical Engineering and Computer Science, Berkeley, CA 94720, 1992.

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Low-Power FPGA Using - Pre-Defined Dual-Vdd Dual-Vt   (Correct)

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E. M. Sentovich et. al., "SIS: A system for sequential circuit synthesis," in Department of Electrical Engineering and Computer Science, Berkeley, CA 94720, 1992.


IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED.. - With Efficient Initial   (Correct)

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E. Sentovich, K. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephan, R. Brayton, and A. Sangiovanni-Vincentelli, "SIS: A system for sequential circuit synthesis," Electron. Res. Lab., Memo. UCB/ERL M92/41, 1992.


Short.. - Deming Chen Jason   (Correct)

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E. Sentovich et al., "SIS: A System for Sequential Circuit Synthesis," Univ. California, Berkeley, CA, Memo. no. UCB/ERL M92/41, 1992.


Power Modeling and Characteristics of Field - Programmable Gate Arrays   (Correct)

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E. M. Sentovich et al., SIS: A system for sequential circuit synthesis. Berkeley, CA: Dept. ECE, Univ. California, 1992.


Output Grouping-Based Decomposition Of Logic - Functions Petr Fiser   (Correct)

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Sentovich, E., M., et al.: SIS: A System for Sequential Circuit Synthesis, Electronics Research Laboratory Memorandum No. UCB/ERL M92/41, University of California, Berkeley, CA 94720, 1992


Structured Design Implementation --- - Strategy For Implementing (1996)   (Correct)

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Sentovich, E.M. et al., "SIS: A System for Sequential Circuit Synthesis", Electr. Res. Lab. Memo No. UCB/ERL M92/41, Dept. of EE and CS, UC Berkeley 4 May 1992


Simplification of Non-Deterministic Multi-Valued Networks - Mishchenko, Brayton (2002)   (Correct)

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E. Sentovich, et al. "SIS: A System for Sequential Circuit Synthesis", Tech. Rep. UCB/ERI, M92/41, ERL, Dept. of EECS, Univ. of California, Berkeley, 1992.


Logic Synthesis for Regular Layout using Satisfiability - Marek Perkowski And (2002)   (Correct)

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E. Sentovich, et al., SIS: A System for Sequential Circuit Synthesis, Tech. Rep. UCB/ERI, M92/41, ERL, Dept. of EECS, Univ. of California, Berkeley, 1992.


Restructuring Multi-Level Networks By Using Function .. - Cortadella.. (2003)   (Correct)

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E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. SangiovanniVincentelli, "SIS: A system for sequential circuit synthesis," U.C. Berkeley, Tech. Rep., May 1992.


Higher-Order Flexibilities in Multi-Valued Networks - Mishchenko, Brayton (2002)   (Correct)

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E. Sentovich, et al. "SIS: A System for Sequential Circuit Synthesis", Tech. Rep. UCB/ERI, M92/41, ERL, Dept. of EECS, Univ. of California, Berkeley, 1992.


A Theory of Non-Deterministic Networks - Alan Mishchenko And (2003)   (Correct)

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E. Sentovich, et al, "SIS: A system for sequential circuit synthesis", Tech. Rep. UCB/ERI, M92/41, ERL, Dept. of EECS, Univ. of California, Berkeley, 1992.


A Theory of Non-Deterministic Networks - Alan Mishchenko And (2005)   (Correct)

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E. Sentovich et al, "SIS: A system for sequential circuit synthesis", Tech. Rep. UCB/ERI, M92/41, ERL, Dept. of EECS, Univ. of California, Berkeley, 1992.


A Boolean Paradigm in Multi-Valued Logic Synthesis - Alan Mishchenko Robert (2002)   (Correct)

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E. Sentovich et al. SIS: A System for Sequential Circuit Synthesis. Tech. Rep. UCB/ERI, M92/41, ERL, Dept. of EECS, Univ. of California, Berkeley, 1992.


Reducing Structural Bias in Technology Mapping - Chatterjee Mishchenko Brayton (2005)   (Correct)

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E. Sentovich, et al. "SIS: A system for sequential circuit synthesis," Tech. Rep. UCB/ERI, M92/41, ERL, Dept. of EECS, U. C. Berkeley, 1992.


Reducing Structural Bias in Technology Mapping - Chatterjee Mishchenko Brayton (2005)   (Correct)

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E. Sentovich, et al. "SIS: A system for sequential circuit synthesis," Tech. Rep. UCB/ERI, M92/41, ERL, Dept. of EECS, U. C. Berkeley, 1992.


A Leakage-aware Low Power Technology Mapping - Algorithm Considering The   (Correct)

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Sentovich, E.M., et al.., SIS: A system for sequential circuit synthesis,. 1992, ERL, University of California, Berkeley.


Technology Mapping for Low Leakage Power and High.. - Effect Consideration ..   (Correct)

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Sentovich, E.M., et al.., SIS: A system for sequential circuit synthesis,. 1992, ERL, University of California, Berkeley.


PMP: Performance-Driven Multilevel Partitioning by Aggregating .. - Hwang, Pedram   (Correct)

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E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, A. SangiovanniVincentelli, `SIS: A System for Sequential Circuit Synthesis', Technical Report UCB/ERL M92/41, Univ. of California, Berkeley, May 1992.


An Exact Solution to Simultaneous Technology Mapping and.. - Lou, Salek, Pedram (1997)   (7 citations)  (Correct)

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E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton and A. Sangiovanni-Vincentelli, "SIS: A System for Sequential Circuit Synthesis", Memorandum No. UCB/ERL M92/41, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720, May 1992.


Efficient Statistical Timing Analysis through Error.. - Khandelwal, Davoodi.. (2004)   (Correct)

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E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, A.L. Sangiovanni-Vincentelli. SIS: A System for Sequential Circuit Synthesis. Memorandum No. UCB/ERL M92/41, Department of EECS. UC Berkeley, May 1992.


Circuit-based Preprocessing of ILP and Its Applications in.. - Chai, Kuehlmann (2004)   (Correct)

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E. Sentovich et al., "SIS: A system for sequential circuit synthesis," Tech. Rep. UCB/ERL M91/41, UC Berkeley, May 1992.


Leakage Control through Fine-Grained Placement and Sizing .. - Khandelwal, Srivastava (2004)   (Correct)

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E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, A.L. Sangiovanni-Vincentelli. SIS: A System for Sequential Circuit Synthesis. Memorandum No. UCB/ERL M92/41, Department of EECS. UC Berkeley, May 1992.


A General Framework for Accurate Statistical Timing.. - Khandelwal, Srivastava (2005)   (Correct)

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E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, A.L. Sangiovanni-Vincentelli. SIS: A System for Sequential Circuit Synthesis. Memorandum No. UCB/ERL M92/41, Department of EECS. UC Berkeley, May 1992.


Temporal Decomposition for Logic Optimization - Nathan Kitchen Andreas (2005)   (Correct)

No context found.

E. Sentovich, K. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephan, R. Brayton, and A. Sangiovanni-Vincentelli, "SIS: A system for sequential circuit synthesis," Memorandum UCB/ERL M92/41, U.C. Berkeley, May 1992.


On Placement and Sizing of Sleep Transistors in Leakage.. - Khandelwal, Srivastava   (Correct)

No context found.

E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, A.L. SangiovanniVincentelli. SIS: A System for Sequential Circuit Synthesis. Memorandum No. UCB/ERL M92/41, Department of EECS. UC Berkeley, May 1992.

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