MICHELI, G. D. 1994. Synthesis and Optimization of Digital Circuits. McGraw-Hill, Inc.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....not violate the dependencies imposed by the transaction partial order. This method has the advantage that it cannot degrade the transaction order since we can discard any solution that is worse. The concept is similar to dynamic variable reordering used in OBDD s (Ordered Binary Decision Diagrams) [ 13]. We have implemented an adaptation to ordered transaction scheduling, called dynamic transaction reordering (DTR) of the Sifting Algorithm introduced by Rudell [17] and have observed that from DTR, we consistently obtain improvements in the iteration period, regardless of the method used to ....

G. De. Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.

....variable (or its complement) is called minterm (such as ##### ) A minimal cover is the set of implicants with minimal cardinality that represents a function. In the previous example, the minimal cover of is . Finding the minimal cover of a SOP formula has been proven to be NP Hard [9]. II. THE IMPLICANT NETWORK The network of Figure 1 implements an arbitrary function ############# ### ####### . At the beginning the network is empty and maps every input to 0. As positive exemplars (minterms) are presented the training algorithm rearranges the Predicate Neurons that ....

....only information already stored in the network without decompressing it. This is a fundamental feature of the algorithm, as information decompression would be intractable in the general case. An n input, single output boolean function can have up to prime implicants and minterms (patterns, [9]) The compression is possible because of a feedback phase, during which, an active predicate neuron is able to find similar nodes to merge with, adjoint to finding those nodes that are already covering its information. This use of the feedback phase is a major contribution of this paper. The ....

G. D. Micheli, Synthesis and Optimization of Digital Circuits. McGrawHill, 1994.

....of them explicitly develops the concept of design decisions or addresses the refinement of a synchronous model into multiple synchronous sub domains as we attempt in this article. In particular the ForSyDe approach allows to use the large amount of work that exists for high level synthesis [33] [77] by defining design decision transformations for refinement techniques like re timing or resource sharing. Voeten points out that each transformational design that is based on a generalpurpose language will suffer from fundamental incompleteness problems [109] This means that the initial model ....

G. D. Micheli. Synthesis and Optimization of Digital Circuits. McGrawHill, 1994.

....Second, as the application complexity increases, automated optimization tools have a better chance to find optimal solution than the programmers. Simple as it may seem, the memory optimization in Figure 1 is rarely performed in traditional software compilers and behavioral synthesis tools [5, 8]. There are a number of reasons which prevent such optimizations from being incorporated, among the most fundamental ones is the difficulty of revealing data dependency information for memory blocks under the presence of pointers. For example, Figure 1 (b) performs the same function as Figure 1 ....

G. D. Micheli. Synthesis and Optimization of Digital Circuits. McGraw Hill, 1994.

....transformations introduced in the paper can cover new search spaces during optimization, thus aiding in area optimization. Research reported is supported by NSF grant MIP 9406946. 1 Introduction Traditional goals in all automatic synthesis and optimization of multi level combinational circuits [13, 11, 10, 8, 7, 9, 22] include minimization of area and performance. While, most of these tools ensure that all faults of interest are testable, random testability [1, 21, 24] of the faults is not considered. As built in self test (BIST) has been widely accepted for testing complex circuits, it is helpful if the goals ....

....y( x) f( x) y( x) j f( x=1) f ( x) y( x) j f( x=0) 1) short notation: y = f:y j 1 f:y j 0 The methodology suggested can be viewed as a two step process : 1. Transformation: y = f:y f:y 2. Reduction: Redundancy elimination. The first step is equivalent to performing a division [22]. Combining it with ATPG based redundancy elimination results in an expansion that can also be seen as special transductions (transformation and reduction) 10] The method to identify divisors is based on indirect implications [19] If a value assignment at a node y allows us to imply a unique ....

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G. De. Micheli, "Synthesis and Optimization of Digital Circuits," McGraw-Hill, Inc. 1994.

....use Shannon s expansion to make gate level connections, based on the above implications. Transformations applied using controllability implications exploit the controllability don t cares in the network, whereas those with observability implications exploit the observability don t cares [9]. For an arbitrary Boolean function, f( x) B 2 B 2 and y( x) B 2 B 2 with B 2 = f0,1g, the following equation holds: y( x) f( x) y( x) j f( x) 1 f( x) y( x) j f( x) 0 (6) Here, we use the following notation, y = f:y j 1 f:y j 0 to represent the above equation. The methodology ....

....(6) Here, we use the following notation, y = f:y j 1 f:y j 0 to represent the above equation. The methodology suggested can be viewed as a two step process : 1. Transformation: y = f:y f:y 2. Reduction: Redundancy elimination. The first step is equivalent to performing a division [9]. Combining it with redundancy elimination results in an expansion that can also be seen as special transductions (transformation and reduction) 6] The method to identify divisors is based on indirect implications [1] If a value assignment at a node y allows us to imply a unique value ....

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G. De. Micheli, "Synthesis and Optimization of Digital Circuits," McGraw-Hill, Inc. 1994.

....problem: structural matching and Boolean matching. In this paper, we propose a fast and simple structural matching algorithm for technology mapping. Boolean matching algorithms are summarized in [1] Structural matching algorithms were originally addressed in [2, 3, 4] and are summarized in [5, 6]. A straightforward method is to match each pattern at each node of the subject Boolean network. A more sophisticated approach is to formulate this matching problem into a string matching problem and to apply existing string matching algorithms, such as the AhoCorasick algorithm [7] to solve the ....

....by a tree is abstracted into a unique index, called the ####### #####. The structural relationships between these structures or substructures are modeled into a lookup table, called the ####### #####. In the past, the relations between patterns have either been ignored, or formed into automata [3, 4, 5] or ContainRelation Graph [8] On the other hand, our lookup table is based on a canonical representation of patterns. Therefore, the problem associated with the traditional approaches, where the large number of possible decomposed patterns results in a signi cant computation cost, is overcome ....

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G. D. Micheli, Synthesis and optimization of digital circuits. McGraw-Hill, Inc., New York, NY, 1994.

....distributed control. Unlike previous approaches, these new transforms can be applied in a systematic way to explore the design space and find optimal distributed controller implementations. The new method starts with a given scheduled and resourcebounded Control Data Flow Graph (CDFG) [18]. Global transforms are first applied to the entire CDFG, unoptimized controllers are then extracted, and, finally, local transforms are then applied to the individual controllers. The result is a highly optimized set of interacting distributed controllers. The transforms include aggressive ....

....is also based on CDFGs, however their method does not do design space exploration, and is limited to handling less concurrent specifications than our approach. As a detailed case study, the transformations are applied to the well known differential equation solver high level synthesis benchmark [26, 18]. A highly optimized asynchronous implementation by Yun et al. 26] was manually designed, using a number of aggressive timing and area based optimizations. Such an implementation cannot be obtained using existing CAD tools. We demonstrate that a very similar optimized design can be simply and ....

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G. D. Micheli. Synthesis And Optimization Of Digital Circuits. McGraw-Hill, 1994.

....by pattern generator. If all the pattern candidates are embedded as fixed blocks and there are many overlaps between candidates, maximum gain and utilization still are not likely to be achieved. The problem is similar to resource allocation on scheduled data flow graph in high level synthesis [10]. Resource allocation problem is resolved by solving graph coloring problem in conflict graph. However, this solution cannot be applied to our defined problem. There are two main differences. First is that overlap does not mean that two resources cannot be chosen to be embedded on the chip. ....

G. D. Micheli, " Synthesis and Optimization of Digital Circuits", McGraw-Hill, 1994.

....compressed or the components in the critical concurrency are serialized according to the resource timing constraints. 61 An important issue while scheduling components is to share the components for operations that are not concurrent. Our compiler uses the resource sharing algorithm described in [2]. The maximum number of times any component can be shared is specified beforehand. This number is determined by the cost associated with sharing the resource (mux, interconnect etc) and is empirically determined. An additional heuristic is used while sharing which attempts to allocate the same ....

....to find a pipeline schedule which has initiation rate equal to the number of memory references, and hence is optimum. By optimum we refer to the fact that the pipeline schedule has the best initiation rate possible. The algorithm in Figure 5. 2 is a variant of the ASAP scheduling algorithm [2]. Statements that are not memory references are scheduled as soon as possible. Statements that are memory references are placed as soon as possible, provided they do not conflict with any already placed memory referencing statement. This is done by assigning the states corresponding to memory ....

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G. D. Micheli, Synthesis and Optimization of Digital Circuits, pg. 185-265, ISBN0 -07-016333-2, McGraw-Hill, Inc.

....by pattern generator. If all the pattern candidates are embedded as fixed blocks and there are many overlaps between candidates, maximum gain and utilization still is not likely to be achieved. The problem is similar to resource allocation on scheduled data flow graph in high level synthesis [6]. In resource allocation problem is resolved by solving graph coloring problem in conflict graph. However, this solution cannot be applied to our defined problem. There are tow main differences. First is that overlap does not mean that two resources cannot be chosen to be embedded on the chip. ....

G. D. Micheli. " Synthesis and Optimization of Digital Circuits", McGraw-Hill, 1994.

....noise. They can be naturally illustrated by the consideration of transient faults. The extension of the technique to delay faults is discussed later in Section 6. Transient fault propagation. The formal conditions of transient fault propagation can be formulated in terms of sensitization [21]. Sensitization of a gate g with respect to signal b captures the conditions under which the value at a gate output depends on the value of b. Formally, when g implements Boolean function F , its sensitization with respect to b is: SensF #b#= dF db . The inverse of gate sensitization ....

G. D. Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, Inc., 1994.

....noise. They can be naturally illustrated by the consideration of transient faults. The extension of the technique to delay faults is discussed later in Section 6. Transient fault propagation. The formal conditions of transient fault propagation can be formulated in terms of sensitization [21]. Sensitization of a gate g with respect to signal b captures the conditions under which the value at a gate output depends on the value of b. Formally, when g implements Boolean function F , its sensitization with respect to b is: SensF (b) dF db . 6 The inverse of gate sensitization ....

G. D. Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, Inc., 1994.

....each operation bound by ASAP and ALAP time step) 3. Reallocation (allocate enough function unit for all of the time steps) 4. Functional unit assignment. 5. Register assignment. 6. Bus assignment. These are the normal techniques as can be found in various literatures as [1] 2] [3]. Most of them are a heuristic algorithm and can not guarantee the optimum solution. Combining many of them together is unlikely to get the optimum solution. We had modified them to match with the Dynamic Ant algorithm. Whenever a decision has to be made and there is not enough information, the ....

Micheli, Giovanni. Synthesis and Optimization of Digital Circuits , McgrawHill, 1994.

.... the specification (which can be handled much more easily) and from a possible allocation of the various components into hardware or software (coming from the partitioning phase) The synthesis of the hardware parts usually takes place according to the classic techniques of logical synthesis (see [Micheli 1994]) Conversely, in embedded systems the synthesis of software parts highlights new problems. A scheduler to manage software parts is nearly always required, due to the need to sequentialize a set of tasks that are generally concurrent in the specification (however, there are some exceptions, as in ....

....algorithms [Shin and Choi 1997] or to develop ad hoc algorithms. This approach is followed, for example, in [Chou et al. 1994] where an algorithm for a feasible scheduling (respecting timing constraints) is developed starting from a specification in Verilog. In [Gupta et al. 1994] and [Gupta and Micheli 1994], starting from a specification in HardwareC, a CDFG is derived; several threads are extracted from it and a scheduling algorithm is proposed. In [Chiodo et al. 1995] a synthesis methodology is proposed which starts from a CFSM specification of the system. Using this specification model it is ....

Micheli, G. D. 1994. Synthesis and optimization of digital circuits. McGraw-Hill.

....in Section 7 demonstrate the procedure and show results unattainable by existing methods. Finally, Section 8 provides some experimental results, and Section 9 presents conclusions and future work. 2 Background and Related Work A completely specified Finite State Machine (FSM) M is defined [16, 6] by the tuple #I,O,S,S 0 , T,F#, where I is the input alphabet, O is the output alphabet, S is the set of states, S 0 #Sis the (set of) initial state(s) T = T (i, s) #S,i #I,s #Sis the transition function, and F = F(i, s) #O,i#I,s#S is the output function. An incompletely specified FSM (ISFSM) ....

....These two fronts have seen considerable progress. Only a few recent attempts have been made to address the more general problem of optimal state minimization. In STAMINA [12] some attention is paid 2 assuming an input encoded implementation 3 Modulo the well known all 0 code issue; see [6]. to implementation complexity, but no attempt at direct nor exact solutions was made. A somewhat more direct approach was taken by Avedillo et al. 1] but results were less than encouraging (they were not even compared with a state reduction tool, but rather with NOVA, a state assignment tool, ....

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G. De Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, 1994.

.... accelerators for scientific computation [Monaghan and Noakes 1992] and general purpose coprocessors [Bertin et al. 1992; Thomas et al. 1991] In addition, advances in high level hardware description languages and synthesis tools have significantly reduced the time for hardware system prototyping [Micheli 1994]. We are currently using VHDL as the hardware description language for development of the simulation models for FAST. Commercial hardware synthesis tools are being used for mapping the VHDL models to the FPGAs. The logic produced by such tools may not be optimal, but the methodology allows complex ....

Micheli, G. 1994. Synthesis and Optimization of Digital Circuits. McGraw-Hill Series in Electrical and Computer Engineering.

....to run the application on this TTA, while c tta represents the realization costs for this TTA (in units to be specified later on) As shown in this figure, the solution space is bounded by a curve connecting so called Pareto points. These points are local optimal solutions; they are defined by [Mic94] A point (t exec ; c tta ) 2 S solutions is a Pareto point ( 8(t; c) 2 S solutions ; t t exec c c tta ) The explorer finds its way through this solution space by iteratively trying different architecture solutions, and letting the software and the hardware subsystems produce relevant ....

Giovanni De Micheli. Synthesis and optimization of digital circuits. McGRAW-HILL, 1994.

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MICHELI, G. D. 1994. Synthesis and Optimization of Digital Circuits. McGraw-Hill, Inc.

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G. D. Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, Inc., 1994.

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G. D. Micheli, Synthesis and Optimization of Digital Circuits. McGrawHill, 1994.

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G. D. Micheli. Synthesis and Optimization of Digital Circuits. McGRAW-HILL, 1994.

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G. D. Micheli, Synthesis and Optimization of Digital Circuits. McGraw-Hill, 1994.

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G. D. Micheli. Synthesis and Optimization of Digital Circuits. McGraw Hill, 1994.

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G. D. Micheli, Synthesis and Optimization of Digital Circuits. McGraw Hill, 1994.

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