MICHELI, G. D. 1994. Synthesis and Optimization of Digital Circuits. McGraw-Hill, Inc.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....not violate the dependencies imposed by the transaction partial order. This method has the advantage that it cannot degrade the transaction order since we can discard any solution that is worse. The concept is similar to dynamic variable reordering used in OBDD s (Ordered Binary Decision Diagrams) [ 13]. We have implemented an adaptation to ordered transaction scheduling, called dynamic transaction reordering (DTR) of the Sifting Algorithm introduced by Rudell [17] and have observed that from DTR, we consistently obtain improvements in the iteration period, regardless of the method used to ....

G. De. Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.

....variable (or its complement) is called minterm (such as ##### ) A minimal cover is the set of implicants with minimal cardinality that represents a function. In the previous example, the minimal cover of is . Finding the minimal cover of a SOP formula has been proven to be NP Hard [9]. II. THE IMPLICANT NETWORK The network of Figure 1 implements an arbitrary function ############# ### ####### . At the beginning the network is empty and maps every input to 0. As positive exemplars (minterms) are presented the training algorithm rearranges the Predicate Neurons that ....

....only information already stored in the network without decompressing it. This is a fundamental feature of the algorithm, as information decompression would be intractable in the general case. An n input, single output boolean function can have up to prime implicants and minterms (patterns, [9]) The compression is possible because of a feedback phase, during which, an active predicate neuron is able to find similar nodes to merge with, adjoint to finding those nodes that are already covering its information. This use of the feedback phase is a major contribution of this paper. The ....

G. D. Micheli, Synthesis and Optimization of Digital Circuits. McGrawHill, 1994.

....of them explicitly develops the concept of design decisions or addresses the refinement of a synchronous model into multiple synchronous sub domains as we attempt in this article. In particular the ForSyDe approach allows to use the large amount of work that exists for high level synthesis [33] [77] by defining design decision transformations for refinement techniques like re timing or resource sharing. Voeten points out that each transformational design that is based on a generalpurpose language will suffer from fundamental incompleteness problems [109] This means that the initial model ....

G. D. Micheli. Synthesis and Optimization of Digital Circuits. McGrawHill, 1994.

....Second, as the application complexity increases, automated optimization tools have a better chance to find optimal solution than the programmers. Simple as it may seem, the memory optimization in Figure 1 is rarely performed in traditional software compilers and behavioral synthesis tools [5, 8]. There are a number of reasons which prevent such optimizations from being incorporated, among the most fundamental ones is the difficulty of revealing data dependency information for memory blocks under the presence of pointers. For example, Figure 1 (b) performs the same function as Figure 1 ....

G. D. Micheli. Synthesis and Optimization of Digital Circuits. McGraw Hill, 1994.

....transformations introduced in the paper can cover new search spaces during optimization, thus aiding in area optimization. Research reported is supported by NSF grant MIP 9406946. 1 Introduction Traditional goals in all automatic synthesis and optimization of multi level combinational circuits [13, 11, 10, 8, 7, 9, 22] include minimization of area and performance. While, most of these tools ensure that all faults of interest are testable, random testability [1, 21, 24] of the faults is not considered. As built in self test (BIST) has been widely accepted for testing complex circuits, it is helpful if the goals ....

....y( x) f( x) y( x) j f( x=1) f ( x) y( x) j f( x=0) 1) short notation: y = f:y j 1 f:y j 0 The methodology suggested can be viewed as a two step process : 1. Transformation: y = f:y f:y 2. Reduction: Redundancy elimination. The first step is equivalent to performing a division [22]. Combining it with ATPG based redundancy elimination results in an expansion that can also be seen as special transductions (transformation and reduction) 10] The method to identify divisors is based on indirect implications [19] If a value assignment at a node y allows us to imply a unique ....

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G. De. Micheli, "Synthesis and Optimization of Digital Circuits," McGraw-Hill, Inc. 1994.

....use Shannon s expansion to make gate level connections, based on the above implications. Transformations applied using controllability implications exploit the controllability don t cares in the network, whereas those with observability implications exploit the observability don t cares [9]. For an arbitrary Boolean function, f( x) B 2 B 2 and y( x) B 2 B 2 with B 2 = f0,1g, the following equation holds: y( x) f( x) y( x) j f( x) 1 f( x) y( x) j f( x) 0 (6) Here, we use the following notation, y = f:y j 1 f:y j 0 to represent the above equation. The methodology ....

....(6) Here, we use the following notation, y = f:y j 1 f:y j 0 to represent the above equation. The methodology suggested can be viewed as a two step process : 1. Transformation: y = f:y f:y 2. Reduction: Redundancy elimination. The first step is equivalent to performing a division [9]. Combining it with redundancy elimination results in an expansion that can also be seen as special transductions (transformation and reduction) 6] The method to identify divisors is based on indirect implications [1] If a value assignment at a node y allows us to imply a unique value ....

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G. De. Micheli, "Synthesis and Optimization of Digital Circuits," McGraw-Hill, Inc. 1994.

....problem: structural matching and Boolean matching. In this paper, we propose a fast and simple structural matching algorithm for technology mapping. Boolean matching algorithms are summarized in [1] Structural matching algorithms were originally addressed in [2, 3, 4] and are summarized in [5, 6]. A straightforward method is to match each pattern at each node of the subject Boolean network. A more sophisticated approach is to formulate this matching problem into a string matching problem and to apply existing string matching algorithms, such as the AhoCorasick algorithm [7] to solve the ....

....by a tree is abstracted into a unique index, called the ####### #####. The structural relationships between these structures or substructures are modeled into a lookup table, called the ####### #####. In the past, the relations between patterns have either been ignored, or formed into automata [3, 4, 5] or ContainRelation Graph [8] On the other hand, our lookup table is based on a canonical representation of patterns. Therefore, the problem associated with the traditional approaches, where the large number of possible decomposed patterns results in a signi cant computation cost, is overcome ....

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G. D. Micheli, Synthesis and optimization of digital circuits. McGraw-Hill, Inc., New York, NY, 1994.

....distributed control. Unlike previous approaches, these new transforms can be applied in a systematic way to explore the design space and find optimal distributed controller implementations. The new method starts with a given scheduled and resourcebounded Control Data Flow Graph (CDFG) [18]. Global transforms are first applied to the entire CDFG, unoptimized controllers are then extracted, and, finally, local transforms are then applied to the individual controllers. The result is a highly optimized set of interacting distributed controllers. The transforms include aggressive ....

....is also based on CDFGs, however their method does not do design space exploration, and is limited to handling less concurrent specifications than our approach. As a detailed case study, the transformations are applied to the well known differential equation solver high level synthesis benchmark [26, 18]. A highly optimized asynchronous implementation by Yun et al. 26] was manually designed, using a number of aggressive timing and area based optimizations. Such an implementation cannot be obtained using existing CAD tools. We demonstrate that a very similar optimized design can be simply and ....

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G. D. Micheli. Synthesis And Optimization Of Digital Circuits. McGraw-Hill, 1994.

....by pattern generator. If all the pattern candidates are embedded as fixed blocks and there are many overlaps between candidates, maximum gain and utilization still are not likely to be achieved. The problem is similar to resource allocation on scheduled data flow graph in high level synthesis [10]. Resource allocation problem is resolved by solving graph coloring problem in conflict graph. However, this solution cannot be applied to our defined problem. There are two main differences. First is that overlap does not mean that two resources cannot be chosen to be embedded on the chip. ....

G. D. Micheli, " Synthesis and Optimization of Digital Circuits", McGraw-Hill, 1994.

....compressed or the components in the critical concurrency are serialized according to the resource timing constraints. 61 An important issue while scheduling components is to share the components for operations that are not concurrent. Our compiler uses the resource sharing algorithm described in [2]. The maximum number of times any component can be shared is specified beforehand. This number is determined by the cost associated with sharing the resource (mux, interconnect etc) and is empirically determined. An additional heuristic is used while sharing which attempts to allocate the same ....

....to find a pipeline schedule which has initiation rate equal to the number of memory references, and hence is optimum. By optimum we refer to the fact that the pipeline schedule has the best initiation rate possible. The algorithm in Figure 5. 2 is a variant of the ASAP scheduling algorithm [2]. Statements that are not memory references are scheduled as soon as possible. Statements that are memory references are placed as soon as possible, provided they do not conflict with any already placed memory referencing statement. This is done by assigning the states corresponding to memory ....

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G. D. Micheli, Synthesis and Optimization of Digital Circuits, pg. 185-265, ISBN0 -07-016333-2, McGraw-Hill, Inc.

....by pattern generator. If all the pattern candidates are embedded as fixed blocks and there are many overlaps between candidates, maximum gain and utilization still is not likely to be achieved. The problem is similar to resource allocation on scheduled data flow graph in high level synthesis [6]. In resource allocation problem is resolved by solving graph coloring problem in conflict graph. However, this solution cannot be applied to our defined problem. There are tow main differences. First is that overlap does not mean that two resources cannot be chosen to be embedded on the chip. ....

G. D. Micheli. " Synthesis and Optimization of Digital Circuits", McGraw-Hill, 1994.

....noise. They can be naturally illustrated by the consideration of transient faults. The extension of the technique to delay faults is discussed later in Section 6. Transient fault propagation. The formal conditions of transient fault propagation can be formulated in terms of sensitization [21]. Sensitization of a gate g with respect to signal b captures the conditions under which the value at a gate output depends on the value of b. Formally, when g implements Boolean function F , its sensitization with respect to b is: SensF #b#= dF db . The inverse of gate sensitization ....

G. D. Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, Inc., 1994.

....noise. They can be naturally illustrated by the consideration of transient faults. The extension of the technique to delay faults is discussed later in Section 6. Transient fault propagation. The formal conditions of transient fault propagation can be formulated in terms of sensitization [21]. Sensitization of a gate g with respect to signal b captures the conditions under which the value at a gate output depends on the value of b. Formally, when g implements Boolean function F , its sensitization with respect to b is: SensF (b) dF db . 6 The inverse of gate sensitization ....

G. D. Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, Inc., 1994.

....each operation bound by ASAP and ALAP time step) 3. Reallocation (allocate enough function unit for all of the time steps) 4. Functional unit assignment. 5. Register assignment. 6. Bus assignment. These are the normal techniques as can be found in various literatures as [1] 2] [3]. Most of them are a heuristic algorithm and can not guarantee the optimum solution. Combining many of them together is unlikely to get the optimum solution. We had modified them to match with the Dynamic Ant algorithm. Whenever a decision has to be made and there is not enough information, the ....

Micheli, Giovanni. Synthesis and Optimization of Digital Circuits , McgrawHill, 1994.

.... the specification (which can be handled much more easily) and from a possible allocation of the various components into hardware or software (coming from the partitioning phase) The synthesis of the hardware parts usually takes place according to the classic techniques of logical synthesis (see [Micheli 1994]) Conversely, in embedded systems the synthesis of software parts highlights new problems. A scheduler to manage software parts is nearly always required, due to the need to sequentialize a set of tasks that are generally concurrent in the specification (however, there are some exceptions, as in ....

....algorithms [Shin and Choi 1997] or to develop ad hoc algorithms. This approach is followed, for example, in [Chou et al. 1994] where an algorithm for a feasible scheduling (respecting timing constraints) is developed starting from a specification in Verilog. In [Gupta et al. 1994] and [Gupta and Micheli 1994], starting from a specification in HardwareC, a CDFG is derived; several threads are extracted from it and a scheduling algorithm is proposed. In [Chiodo et al. 1995] a synthesis methodology is proposed which starts from a CFSM specification of the system. Using this specification model it is ....

Micheli, G. D. 1994. Synthesis and optimization of digital circuits. McGraw-Hill.

....in Section 7 demonstrate the procedure and show results unattainable by existing methods. Finally, Section 8 provides some experimental results, and Section 9 presents conclusions and future work. 2 Background and Related Work A completely specified Finite State Machine (FSM) M is defined [16, 6] by the tuple #I,O,S,S 0 , T,F#, where I is the input alphabet, O is the output alphabet, S is the set of states, S 0 #Sis the (set of) initial state(s) T = T (i, s) #S,i #I,s #Sis the transition function, and F = F(i, s) #O,i#I,s#S is the output function. An incompletely specified FSM (ISFSM) ....

....These two fronts have seen considerable progress. Only a few recent attempts have been made to address the more general problem of optimal state minimization. In STAMINA [12] some attention is paid 2 assuming an input encoded implementation 3 Modulo the well known all 0 code issue; see [6]. to implementation complexity, but no attempt at direct nor exact solutions was made. A somewhat more direct approach was taken by Avedillo et al. 1] but results were less than encouraging (they were not even compared with a state reduction tool, but rather with NOVA, a state assignment tool, ....

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G. De Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, 1994.

.... accelerators for scientific computation [Monaghan and Noakes 1992] and general purpose coprocessors [Bertin et al. 1992; Thomas et al. 1991] In addition, advances in high level hardware description languages and synthesis tools have significantly reduced the time for hardware system prototyping [Micheli 1994]. We are currently using VHDL as the hardware description language for development of the simulation models for FAST. Commercial hardware synthesis tools are being used for mapping the VHDL models to the FPGAs. The logic produced by such tools may not be optimal, but the methodology allows complex ....

Micheli, G. 1994. Synthesis and Optimization of Digital Circuits. McGraw-Hill Series in Electrical and Computer Engineering.

....to run the application on this TTA, while c tta represents the realization costs for this TTA (in units to be specified later on) As shown in this figure, the solution space is bounded by a curve connecting so called Pareto points. These points are local optimal solutions; they are defined by [Mic94] A point (t exec ; c tta ) 2 S solutions is a Pareto point ( 8(t; c) 2 S solutions ; t t exec c c tta ) The explorer finds its way through this solution space by iteratively trying different architecture solutions, and letting the software and the hardware subsystems produce relevant ....

Giovanni De Micheli. Synthesis and optimization of digital circuits. McGRAW-HILL, 1994.

....The life cycle of a variable is the set of control steps during which it is live. Register optimization (also known as register minimization or register sharing) involves grouping variables with disjoint life cycles. Each such group of variables can be safely assigned to the same hardware register [1]. We will use the term carriers to refer to This work was performed at University of Cincinnati and was supported in part by the Advanced Research Projects Agency under order no. 7056 monitored by the Federal Bureau of Investigation under contract no. J FBI 89 094. y With Triquest Design ....

....compatibility relation between pairs of carriers. The problem of finding a minimal set of registers is then modeled as a clique partitioning problem. FACET [2] HAL [10] and CHARM [11] use carrier based techniques for register optimization. Some synthesis researchers, most notably De Micheli, [1] suggested modeling behavioral specifications as hierarchical graphs. In such a representation one can conveniently model loop bodies as modules in the hierarchy as well. Ku and DeMicheli proposed relative scheduling algorithms for hierarchical graphs [12] We use hierarchical modular ....

G. De Micheli, "Synthesis and Optimization of Digital Circuits ", Mc-Graw Hill Inc, 1994.

.... based on precedence constraints, resource binding or assignment is the explicit mapping between the operations and generic resources (functional units) and module selection determines the resource type if more than one resource type can match the functional requirement of an operation type [15]. These three steps are highly dependent on one another. This is due to the fact that operations sharing the same resource must have the same module and that the execution delays of the operations depend on the chosen module. For today s IC systems, the cost of solving the combined scheduling, ....

G. D. Micheli. Synthesis and optimization of digital circuits. McGraw-Hill, Inc, 1994. 27

.... data path can yield optimized 100 single stuck at fault testable fullscan designs [8] An RTL description can also be used to identify the hard to test areas of a design, by analyzing testability ranges and the minimum and maximum number of clock cycles needed to control and observe an RTL node [12]. With RTL testability analysis, a partial scan selection method has been proposed which results in significantly better performance when compared to techniques limited to gate level information only. In [37] an efficient partial scan method is developed to break data path loops. Both register ....

G. De Micheli, "Synthesis and Optimization of Digital Circuits," New York, McGraw-Hill, Inc., 1994.

....The hardware synthesis task for ASICs used in embedded systems (whether they are implemented on FPGAs or not) is generally performed according to the classical high level and logic synthesis methods. These techniques have been worked on extensively; for example, recent books by De Micheli [Mic94] Devadas, Gosh and Keutzer [DGK94] and Camposano and Wolf [CW91] describe them in detail. Marwedel and Goossens [MG95] present a good overview of code generation strategies for DSPs and ASIPs. The software synthesis task for embedded systems, on the other hand, is a relatively new problem. ....

G. De Micheli. Synthesis and optimization of digital circuits. McGraw-Hill, 1994.

....simple heuristics and to results obtained by the SA implementation. Finally, conclusions are enumerated and future work is envisaged. 2. RELATED WORK The development of temporal partitioning algorithms was firstly considered in [9] 1] The similarities of both scheduling on high level synthesis [10] and temporal partitioning allow the use of common scheduling schemes for partitioning. However, an important factor that must be considered is the inter communication (communication among partitions) cost, because it can impose an unacceptable overhead on the overall latency. In [11] a ....

....the median of the relative improvements of SA over ELS. The last row shows the median of each column. In these tests the SA has run over an initial solution obtained by ELS. Table 3. Results for N=100 graphs randomly generated. Out edges t cycles S 2 S 3 S 4 S 5 S 6 S 7 ELS (a,b) SA E 1 ( [0 10] 2 0.9 9.1 1.1 2.2 1.4 9.2 12.2 (2,1) 29.7 19.9 [0 4] 2 1.0 12.4 1.7 3.1 0.8 14.5 18.5 (2,1) 38.1 24 [0 10] 1 0.3 5.8 0.2 0.7 0.7 8.7 6.8 (1,1) 22.9 17.3 [0 4] 1 0.3 7.4 0.7 1.1 3.3 13.7 10.6 (1,1) 28 19.5 [0 10] 0 2.8 8.6 3.5 5.4 8.6 6.0 9.5 (0,1) 13 3.9 [0 4] 0 2.2 11.1 2.9 5.8 16.2 10.8 ....

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G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw Hill, 1994.

.... compiler techniques [5] 6] loop parallelization [7] when real multithreaded is supported, and development of direct execution support (Java microprocessors) 8] Nevertheless all of these efforts can be substantially improved with the integration of HW SW codesign and HighLevel Synthesis (HLS) [9] techniques. Typical HW SW codesign approaches start from a SW specification and migrate SW blocks to HW in order to satisfy timing constrains [10] or to accelerate a generic application in a host by means of HW boards [11] Others begin with an HW specification and migrate to SW some of the HW ....

G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw Hill, 1994.

....that are computed quickly. These bounds are problem speci c and therefore are more e ective in pruning the search space. The e ectiveness of this approach relies on the quality of bounds. Given the number of good heuristics (that produce upper bounds) for scheduling [Camposano and Wolf 1991; De Micheli 1994] and recent results on lower bounds [Rim and Jain 1994; Langevin and Cerny 1996; Narasimhan 1998; Narasimhan and Ramanujam 1997] such an approach is very e ective. We have demonstrated the e ectiveness of this approach by comparing the running times of our algorithm with the time taken to solve ....

De Micheli, G. 1994. Synthesis and Optimization of Digital Circuits. McGraw-Hill.

....at compile time to decide which unroll factor has the most benefit. In contrast, the present approach uses actual execution times and moreover considers loop tiling at the same time. Currently, searching techniques are employed in hardware generation, for example, in design space exploration [14]. In this approach, many implementations of a design are generated and static models are used to estimate for example die size and speed of the circuit. Optimal points in the design space are called Pareto points. For example, one such point signifies that some implementation gives the fastest ....

G. de Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, 1994.

....of the slack available on noncritical paths. 1 Introduction Until recently, the cycle time of digital ICs has been dominated by the delays of the combinational modules. Considerable effort has gone into automatic optimization of the cycle time using techniques such as logic restructuring [1] and gate resizing [2, 3] However, as VLSI fabrication technology reaches deep submicron, interconnect delays are becoming increasingly significant. Today, it is widely reported that in many designs, as much as 50 of the clock cycle is consumed by interconnect delay this delay comes ....

G. D. Micheli, Synthesis and Optimization of Digital Circuits. McGraw Hill, 1994.

....is demonstrated on the example of a 2 bit multiplier. Section 5 includes the experimental results. In the final section, some conclusions are drawn and directions for further research are proposed. 2 Preliminaries We use the standard definitions and notation in the area of logic synthesis ( 12] [17]) The most important notions are briefly summarized in this section. 2.1 Multiple valued input binary valued output functions A multiple valued input, binary valued output function f(x 1 ; x n ) is a mapping f : P 1 Theta P 2 Theta : Theta P n B, where the sets P i = f0; 1; ....

G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.

....and place our work in the context of previous work in those fields. There has been a large body of work on systemlevel synthesis of application specific architectures through HW SW partitioning and mapping of the application tasks onto pre designed cores and application specific hardware [1, 2, 3, 4, 5, 6, 7, 8, 9]. While some of these techniques attempt to consider the impact of communication effects during HW SW partitioning and mapping, they either assume a fixed communication protocol (e.g. PCI based buses) or select from a communication library of a few alternative protocols. Research on ....

....the TCP system ffl Assigning appropriate values for communication protocol parameters (such as priorities and DMA sizes) to the critical events, and translating these results into a high performance implementation. While several techniques have been proposed for system level performance analysis [1, 2] and can be used for the first step, we use an analysis of the system execution traces as a basis for identifying critical communication events. A significant advantage of using execution traces generated through system simulation, is that they can be derived for any system for which a ....

G. De Micheli, Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York, NY, 1994.

....servers or to redistribute to lists, requires prior specific permission and or a fee. DAC 99, New Orleans, Louisiana (c) 1999 ACM 0 89791 920 3 99 06 . 3.50 from the original behavior. Thus, a lot of control flow constructs, which are known to be bottlenecks for various highlevel optimizations [1, 2], are eliminated by considering the CCC alone. ffl In conventional implementations, sharing of CCC operations with non CCC operations may result in a significant amount of additional circuitry and parasitics being associated with the execution of CCCs (e.g. additional multiplexers and control ....

G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, New York, NY, 1994.

....the resulting veri Thetacation algorithm described in the paper, though it can be removed if necessary. This does not require that the loop bodies or boundaries be identical in the two descriptions. We believe that the above assumptions are satis Thetaed by most practical scheduling techniques [8, 9], including well known scheduling algorithms like list, force directed, path based, and loop directed scheduling. We use the term typical scheduling to denote any scheduling algorithm or tool that satis Thetaes these assumptions. As in most approaches, we use loop invariants. However, we do not ....

G. De Micheli, Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York, NY, 1994.

....exist a set of input sequences for which no output is specified. Call such set. Conversely, there exist a set of output sequences which can be produced only by unspecified input sequences. Call such set. The problem of minimizing the number of states in CSFSMs can be solved in polynomial time [10]. For ISFSMs the problem is known to be NP complete [11] Let 0 be an ISFSM and be the set of all possible completely specified implementations of . Thus, for each , every element of and is eventually associated to an element of and , respectively. Let us select an arbitrary sequence and the ....

G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.

....called re encoding has been proposed to reduce the number of rows. To increase the scope of optimization, small TDTs are merged together to produce bigger ones. 5. 1 Behavioral Don t Cares The concept of Don t Cares (DCs) has been extensively used in logic synthesis for gate level optimizations [29, 30, 31]. For synthesis tasks on behavioral descriptions, the notion of Don t Cares is a relatively new concept [32] However, it is believed that a proper definition and use of DCs at higher levels of abstraction will provide a large scope for HDL optimization. In this section, we first introduce the ....

G. D. Micheli, Synthesis and Optimization of Digital Circuits. McGraw-Hill, 1994.

....synthesis takes behavioral models and produces the macroscopic structure of a digital circuit. Compilation techniques used in compiler front end are directly employed to produce behavioral models from HDL descriptions. There are two major tasks in architectural synthesis: scheduling and binding [13]. Scheduling determines the start time of each operation in the algorithmic design at behavioral level. Resource binding maps operations to hardware components. Binding and scheduling are interrelated problems and constrains often complicate the search of a solution. 1.6 Presynthesis ....

G. De Micheli, Synthesis and Optimization of Digital Circuits. McGraw-Hill, 1994.

....are using upper and lower bounding techniques from [LC96] in our implementation, the algorithm is not specific to those techniques. We could just as easily use other lower bounding techniques such as those in [OKD94, FB73b, KP87, RK92, HGC93, HC94] or other upper bounding algorithms (heuristics) De 94, GDWL92, PK89, Pau91, RCJ72, Hu61] 5.6 Experimental Results In this section, the effect of the algorithms on various benchmarks is presented. Since some of these benchmarks are very large, it was not possible to obtain solutions to all instances of the TCS and RCS problems for all the ....

G. De Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, 1994.

....with signal assignments and wait statements in behavioral specifications. 1 Introduction A high level synthesis system generates register level designs to implement the given behavioral specification subject to constraints on area, throughput rate, clock speed and other performance attributes [1, 2, 3, 4, 5]. These designs are synchronous and incorporate two interacting components: a data path and a controller. The primary focus in the area of control synthesis so far, has been in developing efficient techniques for state assignment and output encoding for finite state machines [6] There has been ....

G. De Micheli. "Synthesis and Optimization of Digital Circuits". McGraw-Hill, 1994.

.... computing (RC) concept needs best HW compiler tools [1] to manage the HW complexity nowadays possible to integrate in a Reconfigurable Processing Unit (RPU) 2] The RC systems must integrate the best research efforts in HW SW codesign [3] SW compilation [4] and high level synthesis (HLS) areas [5]. RC architectures provide the capability for spatial parallel computation and so can achieve better speed ups on program execution. However, compilers able to exploit the full potential of the available massive parallelism are needed. Since the proof of concept in [6] there have been few ....

....for each node: ASAP start , ASAP end , ALAP start , and ALAP end ) without resource constraints. The scheduling is based on the delay of each macro cell in fractions of the clock period, previously selected by the user, instead of the control steps as used by coarse grain scheduling schemes [5]. Afterwards, the time interval that an operation node can use without affecting the delay of the critical path is calculated. This time interval is calculated by the equation (1) and represents the sum of the mobility and the delay of the operation. starti endi i ASAP ALAP TI = 1) Based on ....

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G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw Hill, 1994.

....concludes the paper. Supported in part by Research Grant No 240 98 101 from the Swedish Research Council for Engineering Sciences and by a fellowship from the Knut and Alice Wallenbergs foundation of Sweden. 2 Notation We use the standard definitions and notation in the area of logic synthesis ([4]) The most important notions are briefly summarized in this section. Let f(x 1 ; x 2 ; x n ) be an completely specified Boolean function of type f : f0; 1g n f0; 1g, of the variables x 1 ; x n . A point in the domain f0; 1g n of the function f is called a minterm. The ....

G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.

....a conventional synthesis process. However, the methodology requires a tight integration between the synthesis system and a formal verification environment. Formal Verification of RTL designs generated in a conventional high level synthesis environment has long been a challenge. In HLS [3, 8, 14], a behavioral specification goes through a series of transformations leading finally to an RTL design that meets a set of performance goals. A HLS synthesis flow is usually comprised of the following four main stages: ffl The Scheduling Stage: This stage specifies the partial order between the ....

G. De Micheli. "Synthesis and Optimization of Digital Circuits". McGraw-Hill, 1994.

....in the form of a control data flow graph (CDFG) having loops with arbitrary nesting. Various approaches to scheduling in high level synthesis exist [1, 2, 7] Loop scheduling has been addressed in [4, 3] Ku and De Micheli have proposed hierarchical scheduling for real time constraints [5, 6]. In the presence of nested loops, the behavior specification is typically modelled as hierarchical CDFG structure where the CDFG in each level contains two types of nodes: simple nodes representing simple operations such as plus and minus and complex or loop nodes representing a loop structure ....

De Micheli, "Synthesis and Optimization of Digital Circuits", McGraw Hill, 1994.

....to minimizing a given cost function. As with generic Boolean Optimization, BCP also finds many applications, including the computation of minimum size prime implicants, of interest in Automated Reasoning and Non Monotonic Reasoning [16] and as a modeling tool in Electronic Design Automation (EDA) [11, 14]. In recent years, several powerful algorithmic techniques have been proposed for solving BCP, allowing dramatic improvements in the ability to solving large and complex instances of BCP 1 . Despite these improvements, and as with other NP hard problems, new effective techniques allow in ....

D. De Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, 1994.

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MICHELI, G. D. 1994. Synthesis and Optimization of Digital Circuits. McGraw-Hill, Inc.

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G. D. Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, Inc., 1994.

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G. D. Micheli, Synthesis and Optimization of Digital Circuits. McGrawHill, 1994.

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G. D. Micheli. Synthesis and Optimization of Digital Circuits. McGRAW-HILL, 1994.

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G. D. Micheli, Synthesis and Optimization of Digital Circuits. McGraw-Hill, 1994.

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G. D. Micheli. Synthesis and Optimization of Digital Circuits. McGraw Hill, 1994.

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G. D. Micheli, Synthesis and Optimization of Digital Circuits. McGraw Hill, 1994.

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G. De Micheli. Synthesis and Optimization of Digital circuits. McGraw-Hill, 1994.

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G. De Micheli. Synthesis and optimization of digital circuits. McGraw-Hill, New York, 1994.

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