J. Cong, W. Labio, and N. Shivakumar, "Multi-Way VLSI Circuit Partitioning Based on Dual Net Representation," Proceedings of IEEE International Conference on Computer-Aided Design, pp. 56--62, 1994.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....minimized. This problem is known as the module (node) contention problem in the VLSI community. Kahng [37] used a winner loser heuristic [23] whereas Cong et al. 11] used a matching based (IG match) algorithm for solving the 2 way module contention problem optimally. Cong, Labio, and Shivakumar [12] extended this approach to K way HP through using the dual hypergraph model. In the first stage, a K way net partitioning is obtained through partitioning the dual hypergraph. For the second stage, they formulated the K way module contention problem as a min cost max flow problem through defining ....

J. Cong, W. Labio, and N. Shivakumar, "Multi-Way VLSI Circuit Partitioning Based on Dual Net Representation," Proceedings of IEEE International Conference on Computer-Aided Design, pp. 56--62, 1994.

....minimized. This problem is known as the module (node) contention problem in the VLSI community. Kahng [34] used a winner loser heuristic [21] whereas Cong et al. 9] used a matching based (IG match) algorithm for solving the 2 way module contention problem optimally. Cong, Labio, and Shivakumar [10] extended this approach to K way hypergraph partitioning through using the dual hypergraph model. In the first stage, a K way net partitioning is obtained through partitioning the dual hypergraph. For the second stage, they formulated the K way module contention problem as a min cost max flow ....

J. Cong, W. Labio, and N. Shivakumar, "Multi-Way VLSI Circuit Partitioning Based on Dual Net Representation, " Proceedings of IEEE International Conference on Computer-Aided Design, pp. 56--62, 1994.

....compute a k way partitioning directly, rather than via recursive bisection. The most notable of them are the generalization of the FM algorithm for k way partitioning [4, 7] the spectral multi way ratio cut [6] the primal dual algorithm of [5] the geometric embedding [9] the dual net method [12], and the K PM LR algorithm [20] A key problem faced by some of these algorithms is that the k way FM refinement algorithm easily gets trapped in local minima. The recently developed K PM LR algorithm by Cong and Lim [20] attempts to solve this problem by refining a k way partitioning by applying ....

J. Cong, W. Labio, and N. Shivakumar. Multi-way VLSI circuit partitioning based on dual net representation. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pages 396--409, 1996.

....clustering [3] or cell replication [4] 5] 6] to improve the results. Other techniques also exist which effectively solve the multi way partitioning problem, such as spectral methods [7] 8] Boolean programming [9] geometric embeddings [10] placement techniques [11] and others [12] 13] [14]. Approaches that focus on FPGA partitioning, reporting benchmark results, have been proposed in [15] 16] Contributions that address performance oriented partitioning of FPGA are only recent [17] 18] This work addresses and extends the FPGA partitioning problem as defined in [6] 19] 20] ....

J. Cong, W. Labio, and N. Shivakumar. Multi-Way VLSI Circuit Partitioning Based on Dual Net Representation. In IEEE ICCAD-94, pages 56--62, November 1994.

....based on the dual transformation paradigm. Section 4 presents experimental results. We conclude the paper in Section 5 with some observations and directions for future work. An extended abstract of this paper was presented in the 1994 International Conference for Computer Aided Design (ICCAD 94) [12]. 2. Problem formulation Given a netlist NL to be partitioned into K partitions, we use M = m 1 , m 2 , m p to denote the set of modules in NL , N = n 1 , n 2 , n q to denote the set of nets in NL , and P 1 , P 2 , P K to denote the K partitions, where p is the number of ....

J. Cong, W. Labio, and N. Shivakumar, "Multi-Way VLSI Circuit Partitioning Based on Dual Net Representation, " Proc. IEEE Int'l Conf. on Computer-Aided Design, pp. 56-62, Nov. 1994. Also available as UCLA Computer Science Department Tech. Report CSD-940029

.... to compute a series of minimum cuts in the given circuit in order to obtain an area balanced cut with small cut size [YaWo94] The net based partitioning approach first computes a bipartitioning of the nets, and then transforms the net partitioning solution into a module partitioning solution [CoHK92, CoLS96]. The multiway partitioning algorithms include the recursive bipartitioning algorithm by Kernighan and Lin [KeLi70] a generalization of the FM algorithm with lookahead by Sanchis [Sa89] the primal dual algorithm [YeCL91] and a generalization of the graph spectral based partitioning method to ....

.... improvement partitioning algorithms LIFO LA4 (LIFO bucket and modified lookahead formulation based) K DualFM (dual net representation based) GMetis (genetic multi level graph partitioning based) LA3 CDIP (LIFO circuit LIFO LA4 K DualFM GMetis LA3 CDIP CLIP PROPf FM LSRb name size [HaHK95] [CoLS96] [AlHK96] DuDe96] DuDe96] balu 801 27 27 27 27 27 primary1 833 74 52 47 52 51 45 struct 1952 61 38 33 36 33 33 primary2 3014 259 142 152 152 120 s9234 5866 77 43 44 42 43 biomed 6514 165 107 102 83 84 84 s13207 8772 110 74 70 71 58 s15850 10470 93 53 67 56 53 s35932 18148 ....

Cong, J., W. Labio, and N. Shivakumar, "Multi-Way VLSI Circuit Partitioning Based on Dual Net Representation", IEEE Trans. on Computer-Aided Design, pp. 396-409, Apr. 1996

....area balance constraint, and such estimation usually tends to be conservative. In practice, if we relax the area constraint parameter a as defined in Section 2, we can always satisfy condition C1. When condition C1 is true, we have the following results (proofs of these results can be found in [CoLS94]) Lemma The value of the maximum flow in the assignment network is m. Theorem 1 The min cost max flow in the assignment network induces a module assignment whose total preference function is maximum. In fact, it is easy to see that the max flow in the assignment network consists of m edge ....

....zero since n 1 is being cut, and pf (P 1 , m 2 ) should be decreased accordingly. We have developed efficient procedures to update the binding factors and preference functions after each module assignment or re assignment during the flow computation. Details of these procedures can be found in [CoLS94]. It is interesting to note that this dynamic updating of binding factors and preference functions can be easily incorporated in our min cost max flow algorithm after each flow augmentation. Observe that each flow augmenting path assigns one more module to a partition P1 P2 n3 n4 n1 n2 m1 m2 ....

[Article contains additional citation context not shown here]

Cong, J., W. Labio, and N. Shivakumar, "MultiWay VLSI Circuit Partitioning Based on Dual Net Representation," in UCLA Computer Science Department Tech. Report CSD-940029, (Aug. 1994).

.... algorithm to compute a series of minimum cuts in the given circuit in order to obtain an area balanced cut with the smallest cutsize [YW94] The net based partitioning approach first computes a partitioning solution of the nets and then transforms it into a module partitioning solution [CHK92, CLS96] To reduce the computational complexity for partitioning large scale circuits, clustering based methods have been introduced. In this approach, clusters are identified and collapsed, and the resulting clustered circuit is partitioned using existing partitioning methods. Some of the well known ....

....due to its minor perturbation of the current partition compared to an entirely new random initial partition. 4. 2 Comparison to Other Partitioning Algorithms Table 4 shows the comparison of our heap based FM LSRb to state of the art iterative improvement partitioning algorithms K DualFM [CLS96] dual net representation based) GMetis [AHK96] genetic multi level graph partitioning based) LA3 CDIP [DD96] LIFO circuit K DualFM GMetis LA3 CDIP CLIP PROP f FM LSRb name size [CLS96] AHK96] DD96] DD96] CLL 97] balu 801 27 27 27 27 27 primary1 833 52 47 52 51 45 struct 1952 38 ....

[Article contains additional citation context not shown here]

J. Cong, W. Labio, and N. Shivakumar. "Multi-way VLSI circuit partitioning based on dual net representation". IEEE Trans. on Computer-Aided Design, pages 396--409, 1996.

....various constraints such as lower and upper bounds on the area and pin count of each partition. Some of the previous works include recursive KL [9] generalization of FM [10, 11] primal dual [12] spectral multiway ratio cut [3] geometric embedding [2] multilevelbased [8] and dual net based [4] method. There are two primary approaches for generating multiway partitioning solution; recursive or f lat. The recursive approach applies bipartitioning recursively until the desired number of partitions is obtained, whereas the flat approach partitions the circuit directly. We note that cells ....

J. Cong, W. Labio, and N. Shivakumar. Multi-way VLSI circuit partitioning based on dual net representation. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pages 396--409, 1996.

....based on the dual transformation paradigm. Section 4 presents experimental results. We conclude the paper in Section 5 with some observations and directions for future work. An extended abstract of this paper was presented in the 1994 International Conference for Computer Aided Design (ICCAD 94) [CoLS94]. 2. Problem formulation Given a netlist NL to be partitioned into K partitions, we use M = m 1 , m 2 , m p to denote the set of modules in NL , N = n 1 , n 2 , n q to denote the set of nets in NL , and P 1 , P 2 , P K to denote the K partitions, where p is the number of ....

Cong, J., W. Labio, and N. Shivakumar, "Multi-Way VLSI Circuit Partitioning Based on Dual Net Representation," Proc. IEEE Int'l Conf. on Computer-Aided Design, pp. 56-62 , Nov. 1994. Also available -21as UCLA Computer Science Department Tech. Report CSD-940029

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