B. M. Riess, K. Doll and F. M. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques", Proc. ACM/IEEE Design Automation Conf., 1994, pp. 646-651.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....25 medium to large size ACM SIGDA benchmark circuits show up to 70 improvement over FM in mincut, and average mincut improvements of about 35 over all circuits and 47 over large circuits. They also outperform state of the art non IIP techniques, the quadratic programming based method Paraboli [20] and the spectral partitioner MELO [3] by about 17 and 23 , respectively, with less CPU time. This demonstrates the potential of sophisticated IIP algorithms in dealing with the increasing complexity of emerging VLSI circuits. We also compare CLIP and CDIP to hMetis [16] one of the best of the ....

....the space of feasible and thus optimal solutions are different under the two assumptions, and hence the LSR MFFS results are not compatible with those of other partitioners. Delta 4 algorithms: 1) Classical IIP methods (FM [11] and LA [15] 2) State of the art non IIP techniques (Paraboli [20] and MELO [3] and (3) Multilevel IIP algorithms (hMetis [16] Conclusions are in Section 5. 2. PREVIOUS ITERATIVE IMPROVEMENT ALGORITHMS A circuit netlist is usually modeled by a hypergraph G = V;E) where V is the set of cells (also called nodes) in the circuit, and E is the set of nets ....

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B. M. Riess, K. Doll and F. M. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques", Proc. ACM/IEEE Design Automation Conf., 1994, pp. 646-651.

....concerned here with the 2 way min cut partitioning problem. Since 2 way min cut partitioning is NP complete [19] a number of approximate schemes have been proposed. These include iterative improvement methods [16, 17, 23, 24, 29, 30] simulated annealing [31, 32] and clustering based techniques [7, 5, 18, 20, 28, 29, 36, 35]. An excellent survey on partitioning techniques appears in [6] In iterative improvement, we start with a random 2 way partition of the circuit, and iteratively improve it by either swapping pairs of nodes between the subsets, or moving one node at a time between them so that the cutset size is ....

....benchmark suites, which show that PROP performs an average of 30 better than FM and 27 better than LA, while SHRINK PROP obtains about 37 and 34 better results than FM and LA, respectively. We also compare our methods to some of the more recent techniques like EIG1 [20] WINDOW [7] PARABOLI [28], MELO [5] and GMetis [4] Results show that our new techniques also performs significantly better (by 4.5 to 67 ) than these techniques. The rest of this paper is organized as follows. In Sec. 2 we discuss two previous relevant iterative improvement methods FM and LA. Section 3 discusses the ....

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B.M. Riess, K. Doll and F.M. Johannes, "Partitioning very large circuits using analytical placement techniques", Proc. ACM/IEEE Design Automation Conf., 1994, pp. 646-651.

....55 47 s35932 162 47 105 62 49 Geom. Mean 128.5 47.5 112.7 73.1 60.3 Normalized 2.705 1.000 2.373 1.539 1.269 Table 1. Comparison of partitioners. Partitions are between 45 and 55 of total circuit size. FM and Strawman results are from [6] EIG1 results from [1, 7] and Paraboli results from [12]. The various techniques used by Strawman to achieve its superior results are outlined below. A more detailed explanation of these techniques can be found in [6] 3 . Random i nitial partitioning The initial partition is generated by randomly placing nodes into partitions. Size Model The ....

G. M. Riess, K. Doll, F. M. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques", Design Automation Conference, pp. 646-651, 1994.

....bipartitioning techniques, along with some new approaches and optimizations, can yield a bipartitioning algorithm significantly better than the current state of the art. Our algorithm achieved a 8 2 improvement over PROP [Dutt96] 16 improvement over FBB [Yang94] 22 improvement over Paraboli [Reiss94] and MELO [Alpert95b] 50 improvement over Fiduccia Mattheyses [Fiduccia82] and a 58 improvement over EIG1 [Hagen92] Alpert95b] some of the best current bipartitioning algorithms. In this paper, we seek to understand the critical issues in logic replication, the selective duplication of ....

G. M. Riess, K. Doll, F. M. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques", Design Automation Conference, pp. 646-651, 1994.

....or system must be partitioned into subsystems such that elements in the same subsystem are strongly interconnected, whereas elements in different subsystems are weakly interconnected. Such applications include computer logic and page partitioning [16, 23] VLSI layout and packaging of circuits [1, 18, 49, 67], machine layout in manufacturing systems [62, 63] assignment of computations to multiple processors [31] and domain decomposition of finite element or finitevolume grids for parallel computation [3, 22, 53] Both hypergraph and graph K partitioning problems are NP hard, even if edge and vertex ....

B. Riess, K. Doll, and F. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques," in Proceedings 31st ACM/IEEE Design Automation Conference, pp. 646--651, 1994.

....K MFFC FM algorithm, a K FM algorithm based on maximum fanout free cone (MFFC) clustering reported in [10] and show that the resulting algorithm, K DualMFFC FM reduces the net cutsize by 15 to 26 compared with K MFFC FM. Furthermore, we compare the K DualFM algorithm with EIG1[18] and Paraboli [26], two recently proposed spectral based bipartitioning algorithms. We showed that K DualFM reduces the net cutsize by 56 on average when compared with EIG1 and produces comparable results with Paraboli. 1. Introduction The K way partitioning problem is one of partitioning the modules in a ....

.... formulation with the quadratic objective function, which is solved by computing the second smallest eigenvector of the Laplacian matrix of the given network [14, 2, 4, 18] and the use of the linear placement formulation with a linear objective function, which is solved by an iterative method in [26]. The min cut based method uses the maximum flow algorithm to compute a series of minimum cuts in the given circuit in 2order to obtain an area balanced cut with small cut size [29] The net based partitioning approach first computes a bipartitioning of the nets, and then transforms the net ....

[Article contains additional citation context not shown here]

B. M. Riess, K. Doll, and F. M. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques," Proc. ACM/IEEE 31st Design Automation Conf., June 1994.

....25 medium to large size ACM SIGDA benchmark circuits show up to 70 improvement over FM in mincut, and average mincut improvements of about 35 over all circuits and 47 over large circuits. They also outperform state of the art non IIP techniques, the quadratic programming based method Paraboli [20] and the spectral partitioner MELO [3] by about 17 and 23 , respectively, with less CPU time. This demonstrates the potential of sophisticated IIP algorithms in dealing with the increasing complexity of emerging VLSI circuits. We also compare CLIP and CDIP to hMetis [16] one of the best of the ....

....higher level lookahead gains and improved the results for small circuits. All these algorithms improve an initial partition through a sequence of node moves (based on node gains ) and thus fall under the class of iterative improvement partitioners (IIPs) Recently, a number of non IIP algorithms [3, 4, 12, 20, 21] have been proposed and excellent results have been obtained. FM and LA are the most commonly used two way partitioning algorithms largely due to their excellent run times, simple implementations and flexibility. However, this class of IIP algorithms have a common weakness, viz. they only find ....

[Article contains additional citation context not shown here]

B. M. Riess, K. Doll and F. M. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques ", Proc. ACM/IEEE Design Automation Conf., 1994, pp. 646-651.

....results on 25 medium to large size ACM SIGDA benchmark circuits show up to 70 improvement over FM in cutsize, with an average of per circuit percent improvements of about 25 , and a total cut improvement of about 35 . They also outperform the recent placement based partitioning tool Paraboli [13] and the spectral partitioner MELO [14] by about 17 and 23 , respectively, with less CPU time. This demonstrates the potential of iterative improvement algorithms in dealing with the increasing complexity of modern VLSI circuitry. 1. Introduction The essence of VLSI circuit partitioning is to ....

....FM by adding higher level lookahead gains and improved the results for small circuits, while Hagen et al. 15] investigated implementation and tie breaking techniques for improving the performance of FM type algorithms. A number of clustering based, i.e. bottom up, partitioning algorithms [9, 10, 12, 13, 14, 18] have also been proposed and good results have been obtained. FM and LA are the most commonly used two way partitioning algorithms largely due to their excellent run times, simple implementations and flexibility. However, this class of iterative improvement algorithms have a common weakness, ....

[Article contains additional citation context not shown here]

B. M. Riess, K. Doll and F. M. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques", Proc. ACM/IEEE Design Automation Conf., 1994, pp. 646-651.

.... 2 [3, 7, 13, 14] We will thus be concerned here with the 2 way min cut partitioning problem. Since the problem is NP complete, a number of approximate schemes have been proposed. These include iterative improvement methods [3, 6, 9, 10] simulated annealing [12] and clustering based techniques [1, 2, 7, 11, 13, 14]. In iterative improvement methods, we start with a random 2 way partition of the circuit, and iteratively improve it by either swapping pairs of nodes between the subsets, or moving one node at a time between them so that the cutset size is reduced. Clustering based methods try to find natural ....

....to move than either FM or LA.We also run tests on circuit netlists from the ACM SIGDA benchmark, which show that PROP performs an average of 30 better than FM and 27 better than LA. Comparison of PROP to some of the more recent clustering based techniques like EIG1 [7] WINDOW [1] PARABOLI [11] and MELO [2] show that PROP also performs significantly better (by 15 to 57 ) than them. The rest of this paper is organized as follows. In Sec. 2. we discuss two previous iterative improvement methods FM and LA, and thereby set the stage for discussing the PROP technique in Sec. 3. where we ....

[Article contains additional citation context not shown here]

B.M. Riess, K. Doll and F.M. Johannes, "Partitioning very large circuits using analytical placement techniques", Proc. ACM/IEEE Design Automation Conf., 1994, pp. 646-651.

....results on 25 medium to large size ACM SIGDA benchmark circuits show up to 70 improvement over FM in cutsize, with an average of per circuit percent improvements of about 25 , and a total cut improvement of about 35 . They also outperform the recent placement based partitioning tool Paraboli [11] and the spectral partitioner MELO [12] by about 17 and 23 , respectively, with less CPU time. This demonstrates the potential of iterative improvement algorithms in dealing with the increasing complexity of modern VLSI circuitry. 1. INTRODUCTION The essence of VLSI circuit partitioning is to ....

....with respect to the number of pins in the circuit. This is done by moving one cell at a time and using an efficient bucket data structure. Krishnamurthy [4] enhanced FM by adding higher level lookahead gains and improved the results for small circuits. Recently, a number of clustering algorithms [9, 10, 11, 12, 15] have been proposed and excellent results have been obtained. FM and LA are the most commonly used two way partitioning algorithms largely due to their excellent run times, simple implementations and flexibility. However, this class of iterative improvement algorithms have a common weakness, viz. ....

[Article contains additional citation context not shown here]

B. M. Riess, K. Doll and F. M. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques", Proc. ACM/IEEE Design Automation Conf., 1994, pp. 646651.

....module placements. Hall [13] showed that the second eigenvector of the netlist discrete Laplacian yields the natural module ordering for minimum squared wirelength; we call this the EIG1 ordering, following [12] who used this eigenvector for ratio cut partitioning. Recently, Riess et al. [19] have used an analytical conjugate gradient method to construct module orderings according to the linear wirelength objective. Their PARABOLI orderings improve ratio cut partitionings by 50 over EIG1 orderings. Also recently, Alpert and Kahng [2] have induced (one dimensional) module orderings ....

B. M. Riess, K. Doll, and F. M. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques", to appear in Proc. ACM/IEEE Design Automation Conf., San Diego, 1994.

....information about a design, except [ShKu92] and [MuBr91] who incorporate timing information. 4 CLUSTERING METRICS Recently, algorithms based on quadratic programming techniques, also referred to as spectral or eigenvalue based methods, have been presented showing good partitioning results [RiDo94], HaKa91] The general idea of spectral methods is to place the modules into an one dimensional (using one eigenvalue) or n dimensional (two or more eigenvalues) space and group neighbored elements into one part. In conjunction with clustering approaches many different clustering metrics exist, ....

....as described in [FiMa82] With this algorithm we bi partition the clustered MCNC benchmarks and industrial circuits presented in the Chapter 6 using three runs with different starting partitions for each design. We then compare these results (DDP) with already published results from PARABOLI [RiDo94], FM and FMC [CoSm93] FM and RW ST [HaKa92] MBC [Bui89] IG Match [CoHa92] EIG1 IG [HaKa92] EIG1 [HaKa91] and FM and RCut 1.0 [WeCh91] Note that we have transferred results published under primary1 2, which do not use module size information, to primSC1 2 and primGA1 2 respectively. 8 ....

Riess B.M.; Doll K.; Johannes F.M.; "Partitioning Very Large Circuits Using Analytical Placement Techniques", Proc. Design Automation Conf., pp. 646-651, 1994

....use repeated max flow min cut [YaWo94] single [Pla90] or multi commodity [LeRa88] flow techniques for partitioning. Recently, algorithms based on quadratic programming techniques, also referred to as spectral or eigenvalue based methods, have been presented showing good partitioning results [RiDo94], HaKa91] 1 Introduction With continuously rising design complexity partitioning has become a key problem in circuit and system design. Depending on the specific task, partitioning objectives vary: In contrast to iterative improvement algorithms many approaches based on clustering, also known ....

Riess B.M.; Doll K.; Johannes F.M.; "Partitioning Very Large Circuits Using Analytical Placement Techniques", Proceedings of the Design Automation Conference, pp. 646-651, 1994

.... bipartitioning techniques, along with some new approaches and optimizations, can yield a bipartitioning algorithm significantly better than the current state of the art [12] Our algorithm achieved a 8 improvement over PROP [5] 16 improvement over FBB [19] 22 improvement over Paraboli [18] and MELO [2] 50 improvement over Fiduccia Mattheyses [7] and a 58 improvement over EIG1 [10] 2] some of the best current bipartitioning algorithms. In this paper, we seek to understand the critical issues in logic replication, the selective duplication of logic to reduce the resulting ....

G. M. Riess, K. Doll, F. M. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques", Design Automation Conference, pp. 646-651, 1994.

....or system must be partitioned into subsystems such that elements in the same subsystem are strongly interconnected, whereas elements in different subsystems are weakly interconnected. Such applications include computer logic and page partitioning [16, 23] VLSI layout and packaging of circuits [1, 17, 30, 49, 67], machine layout in manufacturing systems [62, 63] assignment of computations to multiple processors [31] and domain decomposition of finite element or finite volume grids for parallel computation [3, 22, 53] Both hypergraph and graph K partitioning problems are NP hard, even if edge and vertex ....

B. Riess, K. Doll, and F. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques," in Proceedings 31st ACM/IEEE Design Automation Conference, pp. 646--651, 1994.

....partitioning algorithms reported in the literature. In particular, it outperforms GMetis [AlHK96] LA3 CDIP [DuDe96] and CLIP PROP f [DuDe96] by 9.7 , 12.7 , and 7.1 , respectively. It also outperforms the state of the art non iterative improvement partitioning algorithm FBB [YaWo94] and Paraboli [RiDJ94] by 17.2 and 30.0 , respectively. 1 Introduction Circuit partitioning divides a given large circuit into a collection of smaller subcircuits, called blocks, to minimize the number of connections among the subcircuits, subject to the balanced area constraint. The partitioning problem is becoming ....

.... formulation with either the quadratic wirelength objective function, which is solved by computing the second smallest eigenvector of the Laplacian matrix of the given circuit [Ba82, Bo87, DoHo73, HaKa92, AlYa95] or a linear wirelength objective function, which is solved by an iterative method in [RiDJ94, LiLC95]. The min cut based method uses the maximum flow algorithm to compute a series of minimum cuts in the given circuit in order to obtain an area balanced cut with small cut size [YaWo94] The net based partitioning approach first computes a bipartitioning of the nets, and then transforms the net ....

[Article contains additional citation context not shown here]

Riess, B. M., K. Doll, F. M. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques", Proc. ACM/IEEE 31st Design Automation Conf., June 1994

....netlists and have integrated a genetic technique that uses previous Metis solutions to help construct new Metis solutions. Our experiments show that this genetic technique produces better results than Metis alone, and in addition, produces cut size that are competitive with previous methods [21] [19] 7] while using less CPU time. 1 Introduction The circuit bipartitioning problem is given as follows: we are given a netlist hypergraph H(V; E) containing n modules V = fv 1 ; v 2 ; v n g; a hyperedge (or net) e 2 E is defined to be a subset of V with size greater than one. A ....

....to generate a solution, but instead of simply generating 100 solutions randomly, we integrate Metis into a genetic algorithm that produces much better average and minimum cuts than Metis alone. Overall our approach generates bipartitioning solutions that are competitive with the approaches of [21] [19] 7] while only requiring a fraction of their runtimes. The rest of our paper is as follows. Section 2 reviews the Metis partitioning package and presents our modifications for circuit netlists. Section 3 discusses the ideas behind our genetic algorithm and how Metis is integrated. Section 4 ....

[Article contains additional citation context not shown here]

B. M. Riess, K. Doll, and F. M. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques", Proc. ACM/IEEE Design Automation Conf., pp. 646-651, 1994.

....components can also reduce the routing resource flexibility needed to satisfy timing and signal integrity constraints. Mahmoud et al. 11] compared the linear and squared wirelength objectives for analog placement and concluded that the linear wirelength objective is superior. Works such as [14] have further shown that a linear wirelength objective can be used to form one dimensional placements that directly yield effective bipartitioning solutions. The 1991 work of Sigl et al. 9, 16] proposed a modification of GORDIAN called GORDIAN L, which optimizes the linear wirelength objective. ....

B. M. Riess, K. Doll and F. M. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques ", Proc. 31st ACM/IEEE Design Automation Conference, 1994, pp. 646--651.

....clustering. By appropriately applying the techniques discussed in this paper, an algorithm based upon KLFM can produce results better than the current state of the art. In Table 10 we present the results of our algorithm (Strawman) along with results of four of the best current methods (Paraboli [Riess94], EIG1 [Hagen92] MELO [Alpert95b] and FBB [Yang94] on a set of standard benchmarks. Those benchmarks beginning with s are the XNF versions of the MCNC partitioning benchmark suite [MCNC93] while the rest were obtained from Charles Alpert s benchmark set [Alpert96] in NET format and ....

....in the context of what has already been discovered. Table 10. Quality comparison of partitioning methods. Values for basic FM and Strawman 2 are the best of ten trials. The EIG1 and MELO results are from [Alpert95b] though EIG1 was proposed in [Hagen92] the Paraboli results are from [Riess94], and the FBB results are from [Yang94] All tests require partition sizes to be between 45 and 55 of the total circuit sizes, and assume that all non I O nodes have unit area. Example Nodes Nets Pins FM EIG1 Paraboli MELO FBB Strawman Time balu 801 735 2697 30 110 41 28 27 36 s1423 831 757 ....

B. M. Riess, K. Doll, F. M. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques", Design Automation Conference, pp. 646-651, 1994.

....subsystem are strongly interconnected, whereas elements in different subsystems are weakly interconnected. Such applications include computer logic and page partitioning (Donath 1988) VLSI layout and packaging of circuits (Alpert and Kahng, 1993; Dunlop and Kernighan, 1985; Hagen and Kahng, 1992; Riess et al. 1994), machine layout in manufacturing systems (Vakharia, 1986) assignment of computations to multiple processors (Hendrickson and Leland, OPTIMAL MODEL BASED DECOMPOSITION OF POWERTRAIN SYSTEM DESIGN 11 1992) and domain decomposition of finite element or finite volume meshes for parallel ....

Riess, B., Doll, K., and Johannes, F., 1994, "Partitioning Very Large Circuits Using Analytical Placement Techniques," Proceedings, 31st ACM/IEEE Design Automation Conference, pp. 646--651.

....it is linearly dependent on total wirelength. On the other hand, a (timing critical) global net (say, O(1000) m in length) will be driven by a larger device and routed (with appropriate spacing and topology) on wider, lower impedance upper layers. Even if the ratio of driver wire resistances as [18] have further shown that a linear wirelength objective can be used to form one dimensional placements that directly yield effective bipartitioning solutions. The 1991 work of Sigl et al. 19] proposed an important modification of GORDIAN, called GORDIAN L, which optimizes the linear wirelength ....

B. M. Riess, K. Doll and F. M. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques", Proc. 31st ACM/IEEE Design Automation Conference, 1994, pp. 646--651.

....a max adjacency approach; cf. Nagamochi and Ibaraki [12] Other constructions been given for VLSI layout. Hall [11] showed that the second eigenvector of the netlist discrete Laplacian yields a minimum squaredwirelength ordering; 10] used this ordering in ratio cut partitioning. Riess et al. [14] used an analytical conjugate gradient method to construct orderings according to a linear wirelength objective. In [3] we induced (one dimensional) orderings via spacefilling curves over multi dimensional spectral netlist embeddings. In the next section, we describe how an iterative graph ....

B. M. Riess, K. Doll, and F. M. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques ", Proc. ACM/IEEE Design Automation Conf., 1994, pp. 646-651.

....from this study is that by appropriately applying existing techniques an algorithm based upon KLFM can produce better results than the current state of the art. In table 1 we present the results of our algorithm (Optimized KLFM) along with results of three of the best current methods (Paraboli [6], EIG1 [7] and Network Flow [8] on a set of standard benchmarks [9] Note that the EIG1 algorithm is meant to be used for ratio cut partitioning, not mincut partitioning as presented here. The results show that our algorithm produces significantly better solutions than the current ....

....105 46 215 91 67 s13207 105 62 241 91 74 s9234 65 45 227 74 70 Mean 118.8 49.8 156.5 73.1 60.3 Normalized 2.386 1.000 3.143 1.468 1.211 Table 1. Quality comparison of partitioning methods. Values for KLFM and Optimized KLFM1 are the best of ten trials. The EIG1 and Paraboli results are from [6] (though EIG1 was proposed in [7] and the Network Flow results are from [8] All tests require partitions between 45 and 55 of the circuit size. In the rest of this paper we discuss the basic KLFM algorithm and compare numerous optimizations to the basic algorithm. This includes methods for ....

B. M. Riess, K. Doll, F. M. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques", DAC, pp. 646-651, 1994.

....algorithms reported in the literature. In particular, it outperforms the state of the art GMetis [AHK96] LA3 CDIP [DD96] and CLIP PROP f [DD96] by 9.7 , 12.7 , and 7.1 , respectively. It also outperforms the state of the art noniterative improvement partitioning algorithms Paraboli [RDJ94] and FBB [YW94] by 30.0 and 17.2 , respectively. viii 1 Introduction Circuit partitioning divides a given circuit into a collection of smaller subcircuits to minimize the number of connections among the subcircuits, subject to the area balance constraint. The partitioning problem is becoming ....

.... placement formulation with either (i) the quadratic wire length objective function solved by computing the second smallest eigenvector of the Laplacian matrix of the given circuit [Bar82, Bop87, DH73, HK92, AY95] or (ii) the linear wire length objective function solved by an iterative method [RDJ94, LLC95] The mincut based method uses the maximum flow algorithm to compute a series of minimum cuts in the given circuit in order to obtain an area balanced cut with the smallest cutsize [YW94] The net based partitioning approach first computes a partitioning solution of the nets and then ....

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B. M. Riess, K. Doll, and F. M. Johannes. "Partitioning very large circuits using analytical placement techniques". In Proc. ACM/IEEE 31st Design Automation Conf., pages 646--651, 1994.

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B. M.. Riess, K. Doll, F. M. Johannes, "Partitioning Very Large Circuits Using Analytical Placement Techniques", DAC, pp. 646-651, 1994.

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