J. Kuskin et al. The Stanford FLASH Multiprocessor. In Proc. of ISCA, pages 302--313, 1994. Home/Search Document Not in Database Summary Related Articles Check |
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A Study on Memory-Based Communications and Synchronization in.. - Matsumoto (2001) (Correct)
....interrupt routines. The MBP performs fine grained communications by using a dedicated hard wired circuit. The Tempest detects fine grained access by the main processors, so interrupts occur too frequently to allow an improved performance for the system as a whole. 2.7. 3 Flash The Flash [29] is the successor to the DASH [31, 30] multiprocessor and includes an integrated protocol processor which detects fine grained access by the main processors to shared blocks and handles the communications required to maintain consistency. Its basic functions are thus similar to those of the MBP, ....
J. Kuskin, D. Ofelt, M. Heinrich, J. Heinlein, R. Simoni, K. Gharachorloo, J. Chapin, D. Nakahira, J. Baxter, M. Horowitz, A. Gupta, M. Rosenblum, and J. Hennessy. The Stanford FLASH Multiprocessor. In Proc. of 21st Int. Symp. on Computer Aarchitecture, pages 302--313, April 1994.
Local Relaxed Consistency Schemes on Shared-Memory Clusters - Schulz, Tao, McKee (Correct)
....system design. No new scheme should require drastic modifications to current processors. While SMP based systems can use the standard MESI like mechanisms in the processors, CC NUMA systems require a significant amount of special hardware in the form of either hardware maintained directories [10], 2] or sharing lists [6] 11] Low hardware complexity. To be feasible, new hardware designs should not significantly deviate from current architectures. For example, the substantial custom hardware required to realize CC NUMA machines is a barrier to more widespread adoption. B. Relaxed ....
J. Kuskin, D. Ofelt, M. Heinrich, J. Heinlein, R. Simoni, K. Gharachorloo, J. Chapin, D. Nakahira, J. Baxter, M. Horowitz, A. Gupta, M. Rosenblum, and J. Hennessy, "The Stanford FLASH Multiprocessor," in In the Proceedings of the 21st International Symposium on Computer Architecture (ISCA), Apr. 1994, pp. 302--313.
SUDS: Automatic Parallelization for Raw Processors - Frank (2003) (Correct)
....interface into constituent primitives. Examples of this from computer architecture include Active Messages as a primitive for building more complex message passing protocols [121] and interfaces that allow user level programs to build their own customized shared memory cache coherence protocols [22, 70, 95]. Examples of the benefits of carefully chosen primitive interfaces are also common in operating systems research for purposes as diverse as communication protocols for distributed file systems [99] virtual memory management [50] and other kernel services [16, 55] The second component of ....
Jeffrey Kuskin, David Ofelt, Mark Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, and John Hennessy. The Stanford FLASH multiprocessor. In Proceedings of the 21st Annual International Symposium on Computer Architecture, pages 302--313, Chicago, Illinois, April 18--21, 1994.
Some Lessons From Using Static Analysis and Software Model.. - Musuvathi, Engler (2003) (6 citations) (Correct)
....three projects. The rst two projects used both static analysis and model checking, while the third used only model checking but sharply re enforced the trade o s we had previously observed. The rst project, described in Section 2 and 3, checked FLASH cache coherence protocol implementation code [24]. We rst used static analysis to nd violations of FLASHspeci c rules (e.g. that messages are sent in such a way as to prevent deadlock) 7] and then, in a follow on work, applied model checking [26] One interesting feature of the This research was supported in part by DARPA contract ....
....coherence protocol implementation code. The next section focuses on the lessons learned from these e orts. Readers familiar with Chou et al. 7] can skip Section 2.1 and 2.2. Readers familiar with Lie et al. 26] can skip Section 2.1 and 2.3. 2. 1 FLASH overview The Stanford FLASH multiprocessor [24] is a scalable cache coherent DSM machine that implements its communication protocols in software that runs on an embedded processor in its programmable node controller, MAGIC. While implementing such protocols in software facilitates great exibility, it places a serious burden on the programmer. ....
J. Kuskin, D. Ofelt, M. Heinrich, J. Heinlein, R. Simoni, K. Gharachorloo, J. Chapin, D. Nakahira, J. Baxter, M. Horowitz, A. Gupta, M. Rosenblum, and J. Hennessy. The Stanford FLASH multiprocessor. In Proceedings of the 21st International Symposium on Computer Architecture, April 1994.
Virtual Clusters: Resource Mangement on Large Shared-Memory.. - Govil (2000) Self-citation (Rosenblum) (Correct)
....in a scalable topology, such as a mesh or a hypercube. Each node contains a few processors, a portion of the globally distributed memory, a node controller, and possibly some I O devices. The node controller handles all memory coherency and I O traffic going through the node. Several research [2, 35, 37] and commercial [18, 36, 39] projects have built sharedmemory multiprocessors based on the above mentioned design. These machines have been available for several years, and are becoming a popular platform in the server market. Besides traditional computation intensive workloads, such as raytrace ....
Jeffrey Kuskin, David Ofelt, Mark Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, and John Hennessy. The Stanford FLASH multiprocessor. In Proceedings of the 21st International Symposium on Computer Architecture (ISCA), pages 302--313, April 1994.
Automatic Partitioning of Data and Computations - Sudarsan Tandri Ibm (Correct)
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J. Kuskin et al. The Stanford FLASH Multiprocessor. In Proc. of ISCA, pages 302--313, 1994.
TAPE: A Transactional Application Profiling Environment - Chi (2005) (Correct)
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J. Kuskin, D. Ofelt, M. Heinrich, J. Heinlein, R. Simoni, K. Gharachorloo, J. Chapin, D. Nakahira, J. Baxter, M. Horowitz, A. Gupta, M. Rosenblum, and J. Hennessy. The Stanford FLASH multiprocessor. In ISCA-21: Proceedings of the 21st International Symposium on Computer Architecture, pages 302--313, 1994.
SmartApps, an Application Centric Approach to High .. - Dang, Garzaran.. (Correct)
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J. Kuskin et al. The Stanford FLASH Multiprocessor. In Proc. of the 21st Annual Int. Symp. on Computer Architecture, pp. 302--313, April 1994.
Coherence Decoupling: Making Use of Incoherence - Huh, Chang, Burger, al. (2004) (1 citation) (Correct)
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J. Kuskin, D. Ofelt, M. Heinrich, J. Heinlein, R. Simoni, K. Gharachorloo, J. Chapin, D. Nakahira, J. Baxter, M. Horowitz, A. Gupta, M. Rosenblum, and J. Hennessy. The Stanford FLASH multiprocessor. In Proceedings of the 21st Int. Symp. on Computer Architecture, pages 302--313, Apr. 1994.
Analytic Evaluation of - Shared-Memory Architectures Daniel (Correct)
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J. Kuskin, D. Ofelt, M. Heinrich, J. Heinlein, R. Simoni, K. Gharachorloo, J. Chapin, D. Nakahira, J. Baxter, M. Horowitz, A. Gupta, M. Rosenblum, and J. Hennessy, "The Stanford FLASH Multiprocessor," Proc. 21st Int'l Symp. Computer Architecture, pp. 302-313, Apr. 1994.
Assessment of Cache Coherence Protocols in Shared-memory.. - Grbic (2003) (Correct)
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Je#rey Kuskin, David Ofelt, Mark Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, and John L. Hennessy. The Stanford FLASH Multiprocessor. In Proceedings of the 21st Annual International Symposium on Computer Architecture, pages 302--313, Chicago, Illinois, June 1994.
Active Memory Clusters: Efficient Multiprocessing on.. - Heinrich, Speight.. (2002) (1 citation) (Correct)
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Kuskin, J., et al.: The Stanford FLASH Multiprocessor. In Proceedings of the 21st International Symposium on Computer Architecture, pages 302--313, April 1994.
Static Analysis Versus Software Model Checking for Bug Finding - Engler, Musuvathi (2004) (4 citations) (Correct)
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Kuskin, J., Ofelt, D., Heinrich, M., Heinlein, J., Simoni, R., Gharachorloo, K., Chapin, J., Nakahira, D., Baxter, J., Horowitz, M., Gupta, A., Rosenblum, M., Hennessy, J.: The Stanford FLASH multiprocessor. In: Proceedings of the 21st International Symposium on Computer Architecture. (1994)
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J. Kuskin, D. Ofelt, M. Heinrich, J. Heinlein, R. Simoni, K. Gharachorloo, J. Chapin, D. Nakahira, J. Baxter, M. Horowitz, A. Gupta, M. Rosenblum, and J. Hennessy, "The Stanford FLASH multiprocessor," in Proc. 21st Int. Symp. Computer Architecture, Chicago, IL, Apr. 1994.
Deriving Efficient Cache Coherence Protocols through.. - Nalumasu, Gopalakrishnan (1997) (1 citation) (Correct)
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J. Kuskin and D. Ofelt et al. The Stanford FLASH multiprocessor. In Proceedings of the 21st Annual International Symposium on Computer Architecture, pages 302--313, May 1994.
Supporting Isolation for Fault and Power Management with.. - Virtualized Memory Systems (Correct)
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J. Kuskin, D. Ofelt, M. Heinrich, J. Heinlein, R. Simoni, K. Gharachorloo, J. Chapin, D. Nakahira, J. Baxter, M. Horowitz, A. Gupta, M. Rosenblum, and J. Hennessy. The Stanford FLASH multiprocessor. In Proceedings of the 21st International Symposium on Computer Architecture, April 1994.
On-Chip Wires: Scaling and Efficiency - Ho (2003) (1 citation) (Correct)
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J. Kuskin et al., "The Stanford FLASH Multiprocessor," Proceedings of the 21st International Symposium on Computer Architecture, pp. 302-13, April 1994.
Static Analysis versus Software Model Checking for Bug Finding - Engler, Musuvathi (2004) (4 citations) (Correct)
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J. Kuskin, D. Ofelt, M. Heinrich, J. Heinlein, R. Simoni, K. Gharachorloo, J. Chapin, D. Nakahira, J. Baxter, M. Horowitz, A. Gupta, M. Rosenblum, and J. Hennessy. The Stanford FLASH multiprocessor. In Proceedings of the 21st International Symposium on Computer Architecture, April 1994.
Cache Coherence Protocol Design for Active Memory Systems - Chaudhuri, Kim, Heinrich (Correct)
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J. Kuskin et al. The Stanford FLASH Multiprocessor. In Proceedings of the 21st International pages 302--313, April 1994.
A Comparison of Software and Hardware Synchronization.. - Carter, Kuo, Kuramkote (1996) (9 citations) (Correct)
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J. Kuskin and D. Ofelt et al. The Stanford FLASH multiprocessor. In Proceedings of the 21st Annual International Symposium on Computer Architecture, pages 302--313, May 1994.
Deriving Efficient Cache Coherence Protocols through.. - Nalumasu, Gopalakrishnan (1997) (1 citation) (Correct)
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J. Kuskin and D. Ofelt et al. The Stanford FLASH multiprocessor. In Proceedings of the 21st Annual International Symposium on Computer Architecture, pages 302--313, May 1994.
Multistriped Addressing - Grossman, Brown, Huang, Knight (2000) (Correct)
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Jeffrey Kuskin, David Ofelt, Mark Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John Hennessy, "The Stanford FLASH Multiprocessor", Proc. ISCA '94, April 1994, pp. 302-313
Coherence Buffer: An Architectural Support for.. - Sarojadevi, Nandy.. (2002) (Correct)
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J. Kuskin, D. Ofelt, M. Heinrich, J. Heinlein, R. Simoni, K. Gharachorloo, J. Chapin, D. Nakahira, J. Baxter, M. Horowitz, A. Gupta, M. Rosenblum, and J. L. Hennessy. The Stanford FLASH Multiprocessor. In Proc. of the 21th Annual Int'l Symp. on Computer Architecture (ISCA'94), pages 302{ 313, April 1994.
A Study on Memory-Based Communications and Synchronization in.. - Matsumoto (2001) (Correct)
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J. Kuskin, D. Ofelt, M. Heinrich, J. Heinlein, R. Simoni, K. Gharachorloo, J. Chapin, D. Nakahira, J. Baxter, M. Horowitz, A. Gupta, M. Rosenblum, and J. Hennessy. The Stanford FLASH Multiprocessor. In Proc. of 21st Int. Symp. on Computer Aarchitecture, pages 302--313, April 1994.
Design and Evaluation of the Hamal Parallel Computer - Grossman (2002) (1 citation) (Correct)
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Jeffrey Kuskin, David Ofelt, Mark Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John Hennessy, "The Stanford FLASH Multiprocessor", Proc. ISCA '94, pp. 302-313.
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