Agarwal, A., Bianchini, R., Chaiken, D., Johnson, K., Kranz, D., Kubiatowicz, J., Lim, B.-H., Mackenzie, K., and Yeung, D. (1995). The MIT Alewife 172 Machine: Architecture and Performance. In Proceedings of the Twenty-Second International Symposium on Computer Architecture.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....based DSM (Distributed Shared Memory) systems. Researchers in computer architecture and DSM have been studying the cache coherence problem for a long time. Many concepts and theories such as several consistency models [35, 22, 16, 21, 7] and numerous practical systems such as the MIT Alewife [2], the Stanford Dash [36] CRL [30] and so on, have been developed to attack the problem. This problem is no different in the field of distributed virtual environments, so we simply borrow the idea from the DSM literature and modify it slightly to fit our specific requirements. This technique is ....

....LP j have a shared copy of s k . To solve these problems, we present a coherence protocol in the following section. 3. 7 Cache Coherence We employ a fixed owner, directory based invalidate protocol similar to that used in many hardware or software based DSM (distributed shared memory) systems [2, 36, 30]. Directory based coherence reduces network traffic because it does not use a broadcast scheme for one LP to send invalidate update messages to all other LPs, which usually generates network traffic that is proportional to the number of LPs squared (M ) Invalidate coherency protocols [28] ....

A. Agarwal, R. Bianchini, D. Chaiken, K. Johnson, D. Kranz, J. Kubiatowicz, B. Lim, K. Mackenzie, and D. Yeung. The MIT Alewife machine: Architecture and performance. Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 2--13, June 1995.

....in a scalable topology, such as a mesh or a hypercube. Each node contains a few processors, a portion of the globally distributed memory, a node controller, and possibly some I O devices. The node controller handles all memory coherency and I O traffic going through the node. Several research [2, 35, 37] and commercial [18, 36, 39] projects have built sharedmemory multiprocessors based on the above mentioned design. These machines have been available for several years, and are becoming a popular platform in the server market. Besides traditional computation intensive workloads, such as raytrace ....

Anant Agarwal, Ricardo Bianchini, David Chaiken, Kirk L. Johnson, David Kranz, John Kubiatowicz, Beng-Hong Lim, Kenneth Mackenzie, and Donald Yeung. The MIT Alewife machine: Architecture and performance. In Proc. of the 22nd Annual Int'l Symp. on Computer Architecture (ISCA'95), pages 2--13, June 1995.

....Such a memory is accessed by special memory operations (loads, stores and swaps) that may depend on the full empty state of the target location and can alter the state. The fine grained synchronization allows the dataflow style of computation. HEP [19] Tera [4, 7] and the MITs Alewife machine [1] are examples of multiprocessors with full empty bit synchronization. Performance results of the MITs Alewife multiprocessor presented in [28] illustrate the advantage of the fine grained synchronization on individual lock free data items (e.g. words) The MITs Alewife machine is a CC NUMA ....

.... types for shared variables similar to data structures with special accessors, such as I structures [5] and M structures [6] used in a programming environment for the MIT Monsoon dataflow machine synchronization in data parallelism programmed for the MIT Alewife shared memory multiprocessor [1]. In EDA, shared variables are of three different synchronization types, I data, X data, and S data, which all impose different constraints in the way accesses may be performed. I data are used for enforcing data 6 dependency: a read operation on an empty variable will lead to suspension, and ....

[Article contains additional citation context not shown here]

A. Agarwal, R. Bianchini, D. Chaiken, K. Johnson, D. Kranz, J. Kubiatowicz, B.-H. Lim, K. Mackenzie, and D. Yeung. The MIT Alewife Machine: Architecture and Performance. In Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA'95), pages 2--13, June 1995.

....it is shown that hardware multithreading can significantly improve processor utilization. A large number of designs have been proposed and or implemented which incorporate hardware multithreading; examples include HEP [Smith81] Horizon [Thistle88] MASA [Halstead88] Tera [Alverson90] April [Agarwal95], and the M Machine [Dally94b] Most of these designs are capable of executing instructions from a different thread on every cycle, allowing even single cycle pipeline bubbles in one thread to be filled by instructions from another. An extreme model of multithreading, variously proposed as ....

Anant Agarwal, Ricardo Bianchini, David Chaiken, Kirk L. Johnson, David Kranz, John Kubiatowicz, Beng-Hong Lim, Kenneth Mackenzie, Donald Yeung, "The MIT Alewife Machine: Architecture and Performance", Proc. ISCA '95, pp. 2-13.

....been incorporated into a variety of academic and commercial operating systems, This work was supported in part by NSF grants numbers EIA 0080124 and CCR 9988361, and by DARPA AFRL contract number F29601 00 K 0182. including Compaq s Tru64, IBM s K42 and multiprocessor Linux systems, the Alewife [1] and Hurricane [18] systems, and parallel real time software from Mercury Computer Systems. Outside the operating system, non scalable test and set locks have come to be widely used in commercially important applications, notably database systems such as Oracle s Parallel Server and IBM s DB2. ....

A. Agarwal, R. Bianchini, D. Chaiken, K. Johnson, D. Kranz, J. Kubiatowicz, B.-H. Lim, K. Mackenzie, and D. Yeung. The MIT Alewife Machine: Architecture and Performance. In Proceedings of the Twenty-Second International Symposium on Computer Architecture, Santa Margherita Ligure, Italy, June 1995.

....One of the suggested notification primitives in this paper extends some of the control over this hardware locking table to external events, such as message arrival notifications from the NI. Several previous systems have advocated moving the NI closer to the CPU. Flash[14] Avalanche [23] Alewife[1], Shrimp[3] and Tempest[21] all placed the NI directly on the system memory bus. Moving the NI to the system bus significantly reduces the cost of accessing the NI over accessing it on a less efficient I O bus. In addition to reducing overhead, placing the NI on the system bus allows these ....

Anant Agarwal, et al. The MIT Alewife Machine: Architecture and Performance. In Proceedings of the 22nd Annual ISCA, 1995, pp. 2-13.

....a number of clients. Autonomous garbage collection can reclaim private data as a strictly local operation without coordinating with other processors [33] Data location management can be important when hardware constraints make shared memory a limited resource [26] Cache coherence overhead [1] can be avoided for private data that only one processor ever sees. Race condition detection [17, 24, 32] need never consider races on private data. Program algorithm documentation can be augmented by compiler validation of programmers claims. Consistency model relaxation allows more aggressive ....

A. Agarwal, R. Bianchini, D. Chaiken, K. Johnson, D. Kranz, J. Kubiatowicz, B.-H. Lim, K. Mackenzie, and D. Yeung. The MIT Alewife machine: Architecture and performance. In Proc. of the 22nd Annual Int'l Symp. on Computer Architecture (ISCA'95), pages 2--13, June 1995.

....and that one can create executions with large numbers of non linearizable operations. Finally, in Section 5 we provide empirical measurements of the extent to which timing can affect linearizability in Bitonic networks and Diffracting trees. These results were collected on a simulated Alewife [1] shared memory multiprocessor using the Proteus [8] simulator. We use our c c2 measure to mathematically support our experimental results: that in a variety of normal situations, the Bitonic counting networks of Aspnes et al. 4] exhibit linearizable behavior. In fact, for high concurrency ....

....violations of timing conditions lead to non linearizability in general counting networks (see Section 6) 5. Empirical evaluation of linearizability We evaluated the linearizability of counting networks on a simulated distributedshared memory machine similar to the MIT Alewife of Agarwal et al. [1]. Alewife is a large scale multiprocessor that supports cache coherent distributed shared memory and user level message passing. The nodes communicate via messages on a two dimensional mesh network. A Communication and Memory Management Unit on each node holds the cache tags and implements the ....

A. Agarwal, R. Bianchini, D. Chaiken, D.K.K. Johnson, J. Kubiatowicz, B.-H. Lim, K. MacKenzie, D. Yeung, The MIT Alewife Machine: architecture and Performance, in: 22nd Internat. Symp. on Computer Architecture, Santa Margherita Ligure, Italy, June 1995, pp. 2-13.

.... earlier designs attempted to use a separate hardware unit for accessing memory, decoupling the memory accesses from pipeline execution [Smith 82] More recently, separate hardware units have been proposed to handle the synchronization among threads in multithreaded architectures (e.g. Alewife [Agarwal 95] StartT NG [Chiou 95] EARTH [Hum 95] PL PS[Kavi 97] We follow this tradition and propose two hardware units for the Scheduled Dataflow (see Figure 2 above although the figure does not show all data paths for Synchronization Processor) One of the hardware units (EP) will be similar to ....

A. Agarwal, et. al. "The MIT Alewife machine: Architecture and performance," Proc. of 22nd Intl. Syrup. on Computer Architecture (ISCA-22), 1995, pp. 2-13.

....Each event queue has a fixed owner, which is defined as the pilot LP of the associated avatar. To implement the shared event queue structure, we use a fixed owner, directorybased invalidate protocol similar to that used in many hardware or software based DSM (distributed shared memory) systems [13, 14, 15]. Directory based coherency reduces network traffic because it does not use a broadcast scheme for one LP to send invalidate update messages to all other LPs, which usually generates network traffic that is proportional to the number of LPs squared (M ) Invalidate coherency protocols [21] ....

Agarwal, R. Bianchini, D. Chaiken, K. Johnson, D. Kranz, J. Kubiatowicz, B. Lim, K. Mackenzie and D. Yeung: "The MIT Alewife Machine: Architecture and Performance" Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 2--13, June 1995.

.... of the earlier designs attempted to use a separate hardware unit for accessing memory, decoupling the memory accesses from pipeline executionIll] More recently, sep arate hardware units have been proposed to handle the synchronization among threads in multithreaded architectures (e.g. Alewife[12], StartT NG[13] EARTH[10] PL PS[14] We follow this tradition and propose two hardware units for the Scheduled Dataflow (see Figure 2 above aJthough the figure does not show all data paths for Synchronization Processor) One of the hardware units (EP) will be similar to conventional RISC ....

A. Agarwal, R. Bianchini, D. Chaiken, K. L. Johnson, D. Kranz, J. Kubiatowicz, B.-H. Lim, K. Mackenzie, ; D. Yeung, The MIT Alewife machine: Architecture and perfor- mance, Proc. of 22nd Int'l Symp. on Computer Architecture ISCA-22), 1995, 2-13.

....transaction cannot be completed and the system could end up in a deadlock. One solution for this problem is to provide enough buffer capacity either by anticipating the worst case scenario or by providing extra buffering in hardware or in main memory (the approach used in the MIT Alewife system [1]) In large systems, providing adequate buffering space could result in underutilization of system resources or could adversely impact system performance. Another solution is to send a negative acknowledge (NACK) whenever there is not enough output buffer space. The third solution is to provide a ....

....implement mmap and munmap system calls. The ioctl interface is used to obtain device infor81 path device description hw . node hub md map Hub memory directory counters hw . node hub io map Hub IO counters hw . node hub ni link alias for the node outgoing link hw . router stat [1 6] link link histogram counters Table 5.5: Device files created by the LKM mation, access link counters, and set device parameters. Table 5.6 shows the ioctl commands implemented by the kernel module and the devices to which they apply. command device description SNPC QUERY Get device ....

AGARWAL, A., BIANCHINI, R., CHAIKEN, D., JOHNSON, K. L., KRANZ, D., KUBIA- TOWICZ, J., LIM, B.-H., MACKENZIE, K., AND YEUNG, D. The MIT Alewife machine: Architecture and performance. In Proceedings of the 22nd International Symposium on Computer Architecture (May/June 1995), pp. 2--13.

....can be made to appear to reside in an I O device of the workstation, in main memory, in cache , or in registers. Different issues arise when the network adaptor emulates each level. Within Aurora, the I O and register (coprocessor) approaches were investigated. Other projects such as Alewife [2] have investigated pseudo caches, and yet others have experimented with pseudomemories. Although the coprocessor approach appears attractive, we learned that it is only suited to a limited range of environments, such as single task embedded applications. In these environments, the receiving or ....

Agarwal, A. et al. "The MIT Alewife Machine: Architecture and Performance," Proceedings of ISCA '95.

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Agarwal, A., Bianchini, R., Chaiken, D., Johnson, K., Kranz, D., Kubiatowicz, J., Lim, B.-H., Mackenzie, K., and Yeung, D. (1995). The MIT Alewife 172 Machine: Architecture and Performance. In Proceedings of the Twenty-Second International Symposium on Computer Architecture.

....that uses both synchronization and data transfer) A shared memory version can outperform the message passing implementation (by up to 14 for our application) under low contention because shared memory offers low overhead data access. Our implementations run on the MIT Alewife multiprocessor [2]. The message passing implementation was ported from a message passing implementation that runs on Thinking Machines CM 5 family of multicomputers [25] The original CM 5 implementation written by Kirk Johnson won first place in an Internet newsgroup contest [14] the goal of which was to solve ....

....shared address space. Each node consists of a Sparcle processor [3] clocked at 20MHz, a 64KB direct mapped cache with 16 byte cache lines, a communications and memory management unit (CMMU) a floating point coprocessor, an Elko series mesh routing chip (EMRC) from Caltech, and 8MB of memory [2]. The EMRCs implement a direct network [24] with a two dimensional mesh topology using wormhole routing [11] A mesh connected SCSI disk array provides I O. Figure 4.1 shows the Alewife architecture. The CMMU implements shared memory and message passing communication interfaces, which will be ....

[Article contains additional citation context not shown here]

A. Agarwal, R. Bianchini, D. Chaiken, K. Johnson, D. Kranz, J. Kubiatowicz, B.-H. Lim, K. Mackenzie, and D. Yeung. "The MIT Alewife Machine: Architecture and Performance." Submitted for publication, December 1994.

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Anant Agarwal, Ricardo Bianchini, David Chaiken, Kirk L. Johnson, David Kranz, John Kubiatowicz, Beng-Hong Lim, Kenneth Mackenzie, and Donald Yeung. The MIT Alewife Machine: Architecture and Performance. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 2--13, Santa Margherita Ligure, Italy, June 1995.

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A. Agarwal, R. Bianchini, D. Chaiken, K. Johnson, D. Kranz, J. Kubiatowicz, B. Lim, K. Mackenzie, and D. Yeung. The MIT Alewife machine: Architecture and performance. In 22nd Annual International Symposium on Computer Architecture, pages 2--13, June 1990.

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A. Agarwal, R. Bianchini, D. Chaiken, and K. L. Johnson. The MIT Alewife Machine: Architecture and Performance. In Proceedings

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Agarwal, A.; Bianchini, R.; Chaiken, D.; Johnson, K.; Kranz, D.; Kubiatowicz, J.; Lim, B.H.; Mackenzie, K. and Yeung, D.: "The MIT Alewife Machine: Architecture and Performance", Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA95), June 1995, pages 2-13

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Agarwal, A.; Bianchini, R.; Chaiken, D.; Chong, F.T.; Johnson, K.L.; Kranz, D.; Kubiatowicz, J.D.; Beng-Hong Lim; Mackenzie, K. and Yeung, D.: "The MIT Alewife Machine: Architecture and Performance", Laboratory for Computer Science, Massachussets Institute of Technology, 1999

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Agarwal, A.: "The MIT Alewife Machine: Architecture and Performance", 25 years of the International Symposia on Computer Architecture (selected papers), Association for Computing Machinery, August 1998, pages 103-110

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A. Agarwal, R. Bianchini, D. Chaiken, K. L. Johnson, D. Kranz, J. Kubiatowicz, B. Lim, K. Mackenzie, and D. Yeung. The MIT Alewife Machine: Architecture and Performance. In Proceedings of the 22nd International Symposium on Computer Architecture, pages 2--13, June 1995.

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A. Agarwal, R. Bianchini, D. Chaiken, K.L. Johnson, D. Kranz, J. Kubiatowicz, Beng-Hong Lim, K. Mackenzie, and D. Yeung. The MIT Alewife machine: Architecture and performance. In Proceedings of the Twenty-Second International Symposium on Computer Architecture, 1995. -

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A. Agarwal, et. al. "The MIT Alewife machine: Architecture and performance", Proc. of 22nd Intl. Symp. on Computer Architecture (ISCA-22), 1995, pp 2-13. 16

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A. Agarwal, R. Bianchini, D. Chaiken, K.L. Johnson, D. Kranz, J. Kubiatowicz, B.H. Lim, K. Mackenzie, and D. Yeung. The MIT alewife machine: Architecture and performance. In Proceedings of the 22 nd International Symposium on Computer Architecture, pages 2--13, Santa Margherita Ligure, Italy, June 1995.

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