Chu, T.-A.: Synthesis of Self-Timed VLSI Circuits from Graph-theoretic Specications, Ph.D. Thesis, MIT, 1987.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....as single transitions showing on inputs , in parallel (at any order) followed by a transition on the output , then followed recursively by again [28] An equivalent signal tran (b) c) Fig. 2. Generalized C elements: a) GC, b) GC RT for a #OE b #, and (c) for a OE b . sition graph (STG) [31], 32] representation of the specification is shown in Fig. 3(a) 1) Relative Timing Synthesis: RT synthesis optimizes a circuit by adding timing arcs to a behavioral specification. Both timing and causality affect the behavior of an RT circuit. Behavioral arcs must be synthesized into gates, ....

T.-A. Chu, "Synthesis of self-timed VLSI circuits from graph-theoretic specifications," Ph.D. dissertation, Massachusetts Institute of Technology, Cambridge, 1987.

....systems. However, StateCharts do not comprise a diagrammatic logic; while they have an operational semantics that allows them to be executed, no inference rules have been defined on them. Chu first proposed Signal Transition Graphs as a graphical representation for specifying asynchronous circuits [22]; their use was extended to verification by Moon [64] No inference rules have been defined on these graphs. Their application to asynchronous systems also sets them apart from HHL, which treats synchronous systems. Sheeran s Ruby is a relational calculus for circuit design that uses pictorial ....

Tam-Anh Chu. Synthesis of Self-timed VLSI circuits from graph-theoretic specfications. PhD thesis, MIT, June 1987.

....gives a more ecient implementation than one large undivided circuit. Decomposition is also useful if it allows to split o a library element; in particular for arbiters, it is valuable to avoid the complicated synthesis of such a circuit and use a known one stored in a library. Chu87a, Chu87b, KKT93] suggest decomposition methods for STGs, but these approaches can only deal with very restricted net classes. Chu87a] only decomposes live and safe free choice nets, which cannot model controlled choices or arbitration, and makes further restrictions; e.g. each transition label is allowed ....

....free choice nets, which cannot model controlled choices or arbitration, and makes further restrictions; e.g. each transition label is allowed only once (which makes the STG deterministic in the sense of language theory) and con icts can only occur between input signals. The conference version [Chu87b] restricts attention even further to marked graphs, which have no con icts at all. The method in [Chu87a, Chu87b] constructs for each output signal s a component C i that generates this signal; C i has as inputs all signals that according to the net structure may directly cause s. The ....

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T.-A. Chu. Synthesis of self-timed VLSI circuits from graph-theoretic speci cations. In IEEE Int. Conf. Computer Design ICCD '87, pages 220-223, 1987.

....composition gives a more ecient implementation than one large undivided circuit. Decomposition is also useful if it allows to split o a library element; in particular for arbiters, it is valuable to avoid the complicated synthesis of such a circuit and use a known one stored in a library. Chu87a, Chu87b, KKT93] suggest decomposition methods for STGs, but these approaches can only deal with very restricted net classes. Chu87a] only decomposes live and safe free choice nets, which cannot model controlled choices or arbitration, and makes further restrictions; e.g. each transition label is ....

....o a library element; in particular for arbiters, it is valuable to avoid the complicated synthesis of such a circuit and use a known one stored in a library. Chu87a, Chu87b, KKT93] suggest decomposition methods for STGs, but these approaches can only deal with very restricted net classes. Chu87a] only decomposes live and safe free choice nets, which cannot model controlled choices or arbitration, and makes further restrictions; e.g. each transition label is allowed only once (which makes the STG deterministic in the sense of language theory) and con icts can only occur between input ....

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T.-A. Chu. Synthesis of Self-Timed VLSI Circuits from GraphTheoretic Speci cations. PhD thesis, MIT, 1987.

....assume that the signals a and b are untimed, but a a b c 0 0 0 0 1 c 1 0 c 1 1 1 (a) b) Fig. 2.3. The Muller C element and its defined behavior. a) The drawn gate symbol with a simple environment. b) The truth table describing the gate s behavior. 18 the signal c has a rising delay of [30, 50] and a falling delay of [25, 45] From this, the earliest firing time relation is Eft = p 1 , t 2 ) 0) p 2 , t 3 ) 0) p 3 , t 4 ) 30) p 4 , t 4 ) 30) p 5 , t 5 ) 0) p 6 , t 6 ) 0) p 8 , t 1 ) 25) p 7 , t 1 ) 25) and the latest firing time relation is Lft ....

....Consider Fig. 2.4(c) that defines the behavior of c. Its transitions are labeled c and c due to the labeling function in the level ruled extension. Similarly, its rules are annotated with timing bounds and Boolean functions. For example, the rule for c includes the bound [30, 50] [25, 45] a) b) c) Fig. 2.4. A Muller C element level ruled Petri net model. a) The specification for input a. b) The specification for input b. c) The specification for output c. 19 [30, 50] for the earliest and latest firing times and the Boolean function a b. The Boolean ....

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T. Chu, Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications. PhD thesis, MIT Laboratory for Computer Science, June 1987.

....of one stage of a pipeline. The environment of this controller corresponds to the previous and next stages of the pipeline. Notice that wire . corresponds to the wire in the previous stage of the pipeline. The behavior of the environment is modeled with Signal Transition Graphs (STG) [6]. Environment events such or describe the rising or falling of signals, and its delay models the time required to fire an event since it becomes enabled in the STG. This asynchronous controller is designed to achieve a very high throughput, so it depends on timing constraints for its correct ....

T.-A. Chu. Synthesis of self-timed VLSI circuits from graph-theoretic specifications. PhD thesis, MIT, June 1987.

....circuits. The events or actions of DI Algebra can be interpreted as signal transitions, and its algebraic laws capture the possibilities of reordering and interference as those transitions are propagated along wires [19] Variants of Petri nets, such as I Nets [15] Signal Transition Graphs [2], or Change Diagrams [11] are popular formalisms for specifying dependences between signal transitions. The petrify tool [4] has been used successfully to synthesise asynchronous circuits from Petri nets. Asynchronous VLSI design teams at the University of Manchester and at Cogency Technology in ....

T.-A. Chu. Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications. PhD thesis, MIT Laboratory for Computer Science, June 1987.

....captures the notions of causality, concurrency and con ict between events. Petri nets have also been chosen by many authors as a formalism to describe the behavior of asynchronous circuits by interpreting the events as signal transitions, thus coining the term Signal Transition Graph (STG) [50, 4]. A design framework for asynchronous systems involves three main aspects: formal speci cation, veri cation and synthesis. In this paper we review the main techniques we have used to cover these aspects in recent years, with a special focus on asynchronous circuits. 1 Introduction The ....

....implementability Checking engineering Reverse Specification (PN) Design is V1 V3 (hazards . Circuit analysis Specification (PN) S1 Top down Bottom up Translation into PN S2 Figure 1: PN usage in design ows The implementability conditions for STGs are known from literature [4, 28, 55]) where they have been formulated in terms of PN markings. Such an approach requires reachability analysis of a PN or an STG, using explicit generation of a reachability graph (or its binary encoded version a State Graph) which can be very complex for a highly concurrent behavior. There are ....

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T.-A. Chu. Synthesis of Self-timed VLSI Circuits from Graph-theoretic Speci cations. PhD thesis, MIT, June 1987.

....design. The method has been automated and applied to a number of examples. 1 Introduction Asynchronous design styles are becoming increasingly popular because they offer the potential benefits of improved system performance, avoidance of clocking problems, low power operation, and modular design [8, 17, 18, 14, 26, 19, 21, 28, 2, 12, 15, 6, 27, 1]. However, the design of correct asynchronous circuitry is a difficult task since an asynchronous circuit can malfunction (i.e. produce unexpected behavior) during execution if it is not free of hazards, which correspond to undesired glitches in a circuit. This is in contrast with synchronous ....

T.-A. Chu. Synthesis of self-timed VLSI circuits from graph-theoretic specifications. Technical Report MIT-LCS-TR-393, Massachusetts Institute of Technology, 1987.

....respectively. 8] has developed grammars (not provably complete, see [9] to specify DI circuits that induce a syntaxdirected translation into a basic set of primitives. 10] uses most of Keller s primitives and some more complex primitives to compile process algebras into DI circuits. [11, 12, 13, 14] have devised practical syn thesis techniques, yet they impose several restrictions on the specification unrelated to delay insensitivity or speed independence and provide very limited means for composing and decomposing DI modules. An automatic compiler in [3] applies some area optimization ....

T.-A. Chu, Synthesis of Self-Timed VLSI Circuits from Graph- Theoretic Specifications. PhD thesis, MIT Laboratory for Computer Science, June 1987.

....datapaths. 2. ASYNCHRONOUS CIRCUITS IN EDA A variety of approaches exist for the design and implementation of asynchronous circuits [5] Transition based approaches specify circuits and systems in terms of signal transitions using Petrinets [11] then using Signal Transition Graphs (STGs) [2] map the specification into an implementable Asynchronous Finite State Machine (AFSM) form. Micropipeline circuits [16] are asynchronous pipelines that may incorporate logic between their stages. Programming compilation approaches [8] 19] start from a circuit specification in a formal language, ....

T. A. Chu. Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications. Technical Report MIT/LCS/TR-393, Massachusetts Institute of Technology, June 1987.

....models. Due to the obvious complexity reasons, the state graph approach is often a serious obstacle for verifying Petri net models of large size. Despite their intuitive simplicity and close link with the existing logic synthesis methods (e.g. from STGs) which are mostly state graph based [9, 2], the state graph techniques often cannot compete in complexity with the causality or net unfolding approach [10] At the same time, the use of the latter for analysis of certain classes of nets (e.g. unsafe or k bounded nets) appears to be in practice not as efficient as desired (see Section 3 ....

....e.g. an STG with a segment which is executed once before it enters its cyclic segment. Such STGs model the behaviour of circuits or signalling protocols with initialisation. STG based synthesis techniques using an assignment of consistent state vectors to the states in the RG have been studied in [14, 2, 9]. They were based on a single consistent state vector to be assigned to every state in the RG, i.e. for any two states of the RG connected with an arc, labelled with a signal transition, the state vectors can differ in only one element which corresponds to the signal involved in the transition. ....

T.A. Chu. Synthesis of Self-Timed VLSI Circuits from Graph-theoretic Specifications. PhD thesis, MIT, 1987.

....of a comparable non hazard free method (espresso exacO. Overhead due to hazard elimination is shown to be negligible. 1 Introduction There has been renewed interest in asynchronous design because of the potential benefits of improved system performance, modular design, and avoidance of clock skew[22, 12, 18, 26, 13, 19, 7, 6, 2, 20, 25, 1]. However, a major obstacle to correct asynchronous design is the problem of hazards, or undesired glitches in a circuit. The elimination of all hazards from asynchronous designs is an important and difficult problem. Many existing design methods do not guarantee freedom from all hazards; other ....

T.-A. Chu. Synthesis of self-timed vlsi circuits from graph-theoretic specifications. Technical Report MIT-LCS-TR-393, 987.

....of how to implement output signals that are produced from circuits constructed from particular types of gate libraries. In [1] networks of gates were used that drove Muller C elements in order to produce each specific output signal. The use of complex gates to drive output signals was promoted in [7] with later work, based on the decomposition of these complex gates, being described in [11] More recently the tool petrify [8] has been designed to take a graph based representation of a circuit as input and produce a synthesized SI circuit as a result. Circuits synthesized using petrify can be ....

....any analysis on this net we need to create what is known as the matrix view of a Petri Net. 4. 2 Matrices and firing sequences STG s and PN s have received much attention over the past few years as being ideal design methodologies for the specification and analysis of asynchronous logic circuits [7, 20, 8]. A PN is a graphical tool that can be used for the analysis of both dynamic and concurrent systems [13] Any PN is a tuple (representing a graph) such that P = S; T ; F; 0 ) where S = the set of vertices that represents the state components (places) of the graph, T = the set of transitions (or ....

T.-A. Chu. Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications. PhD thesis, MIT Laboratory for Computer Science, June 1987.

....which extract more of the available silicon performance, and provide simple and efficient processing rateindependent interfaces. In an attempt to eliminate synchronous operating constraints, numerous asynchronous or self timed logic structures and design styles have been studied and implemented [1, 2, 4, 5, 6, 7, 8, 10, 11, 12, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 26, 27, 28, 29, 30, 32]. Asynchronous or self timed systems promise a number of advantages over traditional synchronous systems: 1. adaptive operation, where the system s performance depends on actual (not worst case) voltage, temperature, process and data; 2. a wider environmental operating range, where the system ....

....external interface of a new asynchronous RISC architecture; and (3) it presents a cache controller which is significantly faster than a comparable synchronous design. Our state machine specification and implementation are substantially more complex than other recent asynchronous examples (cf. [5, 6, 12, 15, 17, 18, 20, 30]) Our design has 16 primary inputs, 19 primary outputs, 4 state variables and 245 product terms in a sum of products implementation. The resulting cache performance using our controller is approximately twice as fast as an equivalent synchronous implementation. 1.1 Background and Previous Work ....

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T.-A. Chu. Synthesis of self-timed VLSI circuits from graph-theoretic specifications. Technical Repor MIT-LCS-TR-393, 1987.

....in [1, 2] Here, Supported by EPSRC grant GR J52327. the key aspects of synchronisation between two pipelines with data flowing in two opposite directions were much easier to define in the form of a state graph. Existing methods and tools for asynchronous hardware design are based on Petri nets [3, 4, 5, 6]. An important task would therefore be to synthesise a Petri net model from a state based description. This and other examples of circuit synthesis, which involve transformations between concurrency models and Petri nets, have been presented in [7] Most of them require passing through the ....

T.-A. Chu. Synthesis of Self-timed VLSI Circuits from Graph-theoretic Specifications. PhD Thesis, MIT, June 1987.

....changes of y 1 is a simple disjunction between the two input arcs . The fi function of all the remaining transitions is AND. Figure 13. b) shows an STD, which is semi modular with respect to all signals. We can thus derive the circuit implementation using any of the existing techniques (e.g. [24, 32, 4, 14, 12]) A set of Boolean functions for the circuit is: We resort to the usual shorthand notation style, in which places are explicitly shown only where they have more than one incoming or outgoing arc. 15 (OR) a) x 1 2 y 1 y x 2 (b) 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 1 1 0 0 0 1 1 0 1 ....

T.A. Chu. Synthesis of Self-Timed VLSI Circuits from Graph-theoretic Specifications. PhD thesis, MIT, 1987.

....of existing (asynchronous) circuits, rather than the design of new circuits from their initial specifications. To our knowledge, the use of PNs and their related formalisms in actual synthesis of hardware has been scarce in the literature. The best known formalism, Signal Transition Graphs (STG) [19, 4], is typically used for the synthesis of asynchronous interface circuits. However, STGs are low level models, and are not really suitable for synthesis of relatively large circuits at a high level of abstraction. While the analysis and synthesis of separate modules is, of course, possible with ....

T.A. Chu. Synthesis of Self-Timed VLSI Circuits from Graph-theoretic Specifications. PhD thesis, MIT, 1987.

....the recognition of the possibility that the CAD tools can be used to to alleviate the designers from being overwhelmed by complex tasks, such as hazard free implementation and critical race free state assignment. As a result, a flurry of new asynchronous design styles and automatic synthesis tools [1, 4, 5, 6, 9, 12, 13, 14, 17, 21, 22] have been introduced to exploit these advantages in system design. There are roughly three distinct categories of asynchronoussynthesismethods available today: Transformations from HDL descriptions [1, 4, 12, 15] STG (Signal Transition Graph) SG (State Graph) synthesis [2, 5, 9, 13, 14, 21] ....

....12, 13, 14, 17, 21, 22] have been introduced to exploit these advantages in system design. There are roughly three distinct categories of asynchronoussynthesismethods available today: Transformations from HDL descriptions [1, 4, 12, 15] STG (Signal Transition Graph) SG (State Graph) synthesis [2, 5, 9, 13, 14, 21], and multiple input change AFSM synthesis [6, 17, 23] Although asynchronous designs have been applied both to data path and control circuits, we believe that the highest payoff will come from applications to interface circuits and controllers. There are two questions we must consider: What is ....

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T.-A. Chu. Synthesis of self-timed VLSI circuits from graph-theoretic specifications. Technical Report MIT-LCS-TR-393, 1987.

....clock and no explicit storage elements. In addition, primary outputs as well as additional state variables are used as feedback variables. Furthermore, the 3D machines do not require state bits to be encoded in the original specification before synthesis can begin; cf. USC CSC property [3, 7, 8, 5, 9, 15]. In this paper, we present an automatic synthesis procedure for the 3D asynchronous state machines; in particular, we describe an algorithm for constructing a three dimensional next state table, a This work was supported by the Semiconductor Research Corporation, Contract no. 91 DJ 205, and by ....

T.-A. Chu. Synthesis of self-timed VLSI circuits from graphtheoretic specifications. Technical Report MIT-LCS-TR-393, 1987.

....controllers. These methods use standard combinational logic, generate low latency outputs and guarantee freedom from hazards at the gate level. Unlike many methods, these methods do not require state bits to be encoded in the original specification before synthesis can begin; cf. USC property [3, 6, 4, 7]. Background. There have been a number of asynchronous design styles in the past 30 years. Many are based on Petri nets [3, 6, 4, 7] or high level languages of concurrency [5] These methods have proved successful for small, highly concurrent designs. However, they often lack flexibility in ....

....the gate level. Unlike many methods, these methods do not require state bits to be encoded in the original specification before synthesis can begin; cf. USC property [3, 6, 4, 7] Background. There have been a number of asynchronous design styles in the past 30 years. Many are based on Petri nets [3, 6, 4, 7] or high level languages of concurrency [5] These methods have proved successful for small, highly concurrent designs. However, they often lack flexibility in minimization and encoding of state and in the implementation of logic functions, and thus have difficulty taking advantage of global ....

T.-A. Chu. Synthesis of self-timed VLSI circuits from graph-theoretic specifications. Technical RepotX MIT-LCS-TR-393, t987.

....to synthesis of speed independent circuits from their formal behavioural specifications. One of the most popular specification languages is Signal Transition Graphs (STGs) that are Petri nets (PNs) whose transitions are labelled with the names of rising and falling edges of circuit signals [2, 18]. Circuit synthesis methods based on STGs can be classified into two major groups. The first group includes those based on a State Graph (SG) which is the Reachability Graph (RG) of an STG (strictly speaking of the PN underlying the STG) encoded with binary vectors corresponding to the states of ....

....Signal Transition Graph and State Coding Problems A Petri net (PN) is a quadruple PN = hP; T; F; m o i, with sets of places P , transitions T , flow relation F and initial marking m o . A marking m is represented with a number of tokens m(p) in each place p 2 P . A Signal Transition Graph (STG) [18, 2] is a triple N = hPN; A; i, where PN is a PN, A = I [ O is a set of signals partitioned into input and output signals, and : T A Theta f ; Gammag is a labelling function that assigns a signal edge name to each transition in T . An STG is thus a labelled PN, specialised to describing the ....

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T.-A. Chu. Synthesis of Self-timed VLSI Circuits from Graph-theoretic Specifications. PhD thesis, MIT, June 1987. 26

....a state change. Both implementations were simulated in all operating modes using the Verilog simulator. The implementations were functionally correct and free of all glitches. Note that the SCSI implementation in particular is significantly larger than designs described in other recent work [3, 5, 8, 9]. However, the worst case latency of the machine under typical operating conditions is only 4ns, and a machine cycle is completed in less than 9.3ns. 6 Conclusions. We have succesfully implemented and simulated two real industry standard controllers using locally clocked asynchronous state ....

T.-A. Chu. Synthesis of self-timed vlsi circuits from graphtheoretic specifications. Technical Report MIT-LCS-TR-393, 1987.

....(SI) circuit is one which assumes that gate de lays are unbounded but wires have negligible delay compared to gates. SI circuits were pioneered by Muller (see [75] and subsequently, there has been significant work both on the theoretical and practical aspects of SI and QDI circuits [32, 6, 55, 25, 74, 90, 67]. The advantage of QDI and SI circuits over DI circuits is that they can be technology mapped to libraries of basic gates like AND, OR, NAND, NOR, etc. However, the circuits must be carefully laid out so that the isochronic fork assumption or zero wire delay assumption is met. A large number of ....

T.-A. Chu. Synthesis of Self-timed VLSI Circuits from Graph-Theoretic Specifica- tions. PhD thesis, MIT, 1987. Technical Report MIT-LCS-TR-393.

....management, high peak power dissipation, worst case design requirements, etc. Many have been advocating asynchronous design as a possible solution to these problems. As a result, there have been many recent advances in asynchronous design techniques, particularly in the area of automated synthesis [1, 15, 4, 8, 10, 12, 13, 17]. There have been some attempts at real system designs employing asynchronous techniques as well [16, 2, 5, 7, 11] It is becoming increasingly clear that system designers recognize asynchronous design as a viable alternative to strictly syn This research was supported in part by a gift from ....

Tam-Anh Chu. Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications. PhD thesis, MIT Laboratory for Computer Science, June 1987.

....design tool ATACS. In ATACS, the design of timed circuits begins with a speci cation of circuit behavior in a hardware description language including VHDL, timed handshaking expansions (THSE) 63, 86] asynchronous nite state machines (AFSM) 42, 32, 84] and signal transition graphs (STG) [28]. These speci cation methods are able to describe sequencing, concurrency, and choice. Moreover, they support bounded timing information which is used to optimize the circuit implementations during various design stages. The timing parameters can come from the simulation of similar designs; or ....

....and needs a lot of human intervention to work e ectively. Graph based approaches often specify circuit behavior in a lower level. It can often produce very ecient and fast circuits since timing information can be used to optimize the implementations. Graph based methods include Petri Nets or STGs [28], I nets [57] change diagrams [81] asynchronous nite state machines [42, 32, 84] and state graphs [60] These methods often require complete state space exploration to nd all reachable states in a design. Therefore, the state space explodes quickly as the complexity and size of the designs ....

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Chu, T.-A. Synthesis of Self-Timed VLSI Circuits from Graph-theoretic Specications. PhD thesis, Massachusetts Institute of Technology, 1987. 122

....(SI) circuit is one which assumes that gate delays are unbounded but wires have negligible delay compared to gates. SI circuits were pioneered by Muller (see [75] and subsequently, there has been significant work both on the theoretical and practical aspects of SI and QDI circuits [32, 6, 55, 25, 74, 90, 67]. The advantage of QDI and SI circuits over DI circuits is that they can be technology mapped to libraries of basic gates like AND, OR, NAND, NOR, etc. However, the circuits must be carefully laid out so that the isochronic fork assumption or zero wire delay assumption is met. A large number of ....

T.-A. Chu. Synthesis of Self-timed VLSI Circuits from Graph-Theoretic Specifications. PhD thesis, MIT, 1987. Technical Report MIT-LCS-TR-393.

....when a high degree of concurrency is involved. Several tools have been generated for the automatic verification of asynchronous circuits with event based formalisms [15, 16] Examples of event based formalisms are Trace Theory [17 19] DI Algebra [20] Petri nets, and Signal Transition Graphs [21, 22]. 3 Design Techniques This section introduces the most popular types of asynchronous circuits and briefly describes some of their design techniques. 3.1 Types of Asynchronous Circuits There are special types of asynchronous circuits for which formal and informal specifications have been given. ....

....Circuits and STG synthesis Speed independent circuits are usually designed by a form of Petri nets [35] A popular version of Petri nets, signal transition graphs (STG) was introduced by Chu. He also developed a synthesis technique for transforming STGs into speed independent circuits [21]. Chu s work 11 was extended by Meng, who produced an STG based tool for synthesizing speed independent circuits from high level specifications [36] In this technique, a circuit is composed of computational blocks and interconnection blocks. Computational blocks range from a simple shifter ....

T.-A. Chu, Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications. PhD thesis, MIT Laboratory for Computer Science, June 1987.

....been applied to several large scale control and data path circuits and microprocessors [14] 22] 15] 23] 35] 39] 20] 2] A number of methods have been developed for the design of asynchronous controllers. Much of the recent work has focused on Petri Net based methods [18] 1] 16] [5], 40] 6] 7] and burst mode methods [27] 9] 25] 43] 17] 31] 13] These two classes of design methods differ in fundamental aspects: the delay model and how the circuit interacts with its environment [10] Petri Net based methods typically synthesize circuits to work correctly ....

T.-A. Chu, "Synthesis of self-timed VLSI circuits from graph-theoretic specifications," Ph.D. dissertation, MIT Laboratory for Computer Science, Cambridge, June 1987.

...., s 0 =# v a #s#=1 v a #s 0 #=0 s b# , s 0 a 6= b =# v a #s#=v a #s 0 # 3.2. 2 Signal Transition Graph A Signal Transition Graph (STG) is a Petri net in which transitions are labeled with the same type of events that we defined for SGs, i.e. rising and falling signal transitions [4]. An STG has an associated SG in which each reachable marking corresponds to a state and each transition between a pair of markings corresponds to an arc labeled with the same event as that labeling the transition. Although STGs with bounded reachability space and SGs have the same descriptive ....

T.-A. Chu. Synthesis of Self-timed VLSI Circuits from Graphtheoretic Specifications. PhD thesis, MIT, June 1987.

....to synthesis of speed independent circuits from their formal behavioural specifications. One of the most popular specification languages is Signal Transition Graphs (STGs) that are Petri nets (PNs) whose transitions are labelled with the names of rising and falling edges of circuit signals [1, 17]. Circuit synthesis methods based on STGs can be classified into two major groups. The first group includes those based on a State Graph (SG) which is the Reachability Graph (RG)ofan STG (strictly speaking of the PN underlying the STG) encoded with binary vectors corresponding to the states of ....

....in its particularly critical part: to find a more accurate way of determining actual coding conflicts in the STG unfolding. A state coding conflict occurs when a pair of different states in a specification has the same binary encoding (this is called Complete State Coding (CSC) conflict [1]) Such conflicts are tentatively identified by means of a conservative estimation of the state space, via place cover cubes. Some of these conflicts may not be actual CSC conflicts, thus leading to the two main contributions of the paper: 1. Conditions to determine whether a particular state ....

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T.-A. Chu. Synthesis of Self-timed VLSI Circuits from Graph-theoretic Specifications.PhD thesis, MIT, June 1987.

....concurrent systems. By labeling transitions with symbols from a given alphabet, transitions can be interpreted as the occurrence of events or the execution of tasks in a system. Labeled Petri Nets have been used in numerous applications: design and specifications of asynchronous circuits [53] [12], 34] 32] resource allocation in operating systems and distributed computation [55] analysis of concurrent programs [50] performance analysis and timing verification [29] 52] and high level design [23] Petri Nets are popular due to their inherent ability to express concurrency, choice ....

# T.-A. Chu, "Synthesis of Self-Timed VLSI Circuits from GraphTheoretic Specifications," PhD thesis, Massachusetts Inst. of Technology, June 1987.

....and vice versa, then a latch controller is said to be semi decoupled. Table 1 contrasts the performance and circuit size (in numbers of transistors) of the semi and fully decoupled latch controllers described in [7] and implemented using the Signal Transition Graph (STG) circuit design approach [10] and of those implemented using directmapped AFSMs. Performance is contrasted by measuring the delays of the handshake signals of unloaded latchcontrollers, i.e. without a buffer and a data register. The columns labeled STG illustrate the delays of the circuit realised using the Signal ....

T. A. Chu, "Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications," Tech. Rep. MIT/LCS/TR-393, Massachusetts Institute of Technology, June 1987.

.... 0 ) 1 s a Gamma Gamma s 0 = va(s) 1 va(s 0 ) 0 s b Gamma s 0 a 6= b = va(s) va(s 0 ) A Signal Transition Graph (STG) is a Petri net in which transitions are labeled with the same type of events we have defined for SGs, i.e. rising and falling signal transitions [3, 11]. An STG has an associated SG in which each reachable marking corresponds to a state and each transition between a pair of markings to an arc labeled with the same event of the transition. Although STGs with bounded reachability space and SGs have the same descriptive power, STGs can usually ....

T.-A. Chu. Synthesis of Self-timed VLSI Circuits from Graphtheoretic Specifications. PhD thesis, MIT, June 1987.

....difficult. Asynchronous systems, free from the clock, offer a number of potential advantages, such as reduced risk of synchronization failures, low power consumption, improved noise and electromagnetic compatibility to name but a few. Interpreted PNs (called Signal Transition Graphs (STGs) [2, 7]) are widely used in specifying an asynchronous system behavior in a formal timing diagram style. It is known that from an STG one can derive an implementation which has the speed independent (SI) property, i.e. such that the behavior of the circuit is correct under any distribution of gate ....

....are interpreted as signal transitions: rising transitions of signal # are labeled with ## and falling transitions with ## . We also use the notation ## if we are not specific about the sign of the transition. Petri Nets with such an interpretation are called Signal Transition Graphs (or STGs) [2]. STGs are typically represented in a shorthand form, where places with one input and one output arc are implicit. An STG transition is enabled if all its input places contain a token. In the initial marking ####### of the STG in Figure 1.c transition ### ### # is enabled. Every enabled ....

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T.-A. Chu. Synthesis of Self-timed VLSI Circuits from Graphtheoretic Specifications. PhD thesis, MIT, June 1987.

....= v a (s) 1 v a (s 0 ) 0 s b Gamma s 0 a 6= b = v a (s) v a (s 0 ) 3.2. 2 Signal Transition Graph A Signal Transition Graph (STG) is a Petri net in which transitions are labeled with the same type of events that we defined for SGs, i.e. rising and falling signal transitions [4]. An STG has an associated SG in which each reachable marking corresponds to a state and each transition between a pair of markings corresponds to an arc labeled with the same event as that labeling the transition. Although STGs with bounded reachability space and SGs have the same descriptive ....

T.-A. Chu. Synthesis of Self-timed VLSI Circuits from Graphtheoretic Specifications. PhD thesis, MIT, June 1987.

....is an input to our algorithm. This is followed by the description of our algorithm together with experimental results. Finally, we state our conclusions. DETERMINISTIC STG In this section, we de ne a deterministic STG representation which is a subset of the STG representation devised by Chu[4]. De nition 1 A Petri net is de ned as the four tuple P; T ; F; M 0 , where P denotes a set of places, T denotes a set of transitions, F denotes the ow relation F (P T ) T P ) and M 0 denotes an initial marking. Here, a marking is a mapping which assigns a non negative integer ....

T.A. Chu, \Synthesis of Self-timed VLSI Circuits from Graph Theoretic Speci cations", Ph.D. Thesis, Massachusetts Institute of Technology, 1987.

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Chu, T.-A.: Synthesis of Self-Timed VLSI Circuits from Graph-theoretic Specications, Ph.D. Thesis, MIT, 1987.

No context found.

T.-A. Chu. Synthesis of self-timed VLSI circuits from graph-theoretic specifications. PhD thesis, MIT, 1987.

No context found.

T.-A. Chu. Synthesis of Self-Timed VLSI Circuits from Graph-theoretic Specifications. P. D. Thesis, MIT, 1987.

No context found.

T.-A. Chu. Synthesis of Self-Timed VLSI Circuits from Graph-theoretic Specifications. P. D. Thesis, MIT, 1987.

No context found.

T.A. Chu. Synthesis of Self-timed VLSI Circuits from Graph-theoretic Specifications. Phd thesis, MIT, 1987.

No context found.

Chu, T.-A.: Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications, Ph.D. Thesis, Laboratory for Computer Science, Massachusetts Institute of Technology, 1987.

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Tam-Anh Chu. Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications. PhD thesis, MIT Laboratory for Computer Science, June 1987.

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T. Chu, "Synthesis of Self-timed VLSI Circuits from Graph-theoretic Specifications", in Proc. of the International Conference on Computer Design (ICCD), pp. 220-223, 1987.

No context found.

Chu, T.-A.: Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications, Ph.D. Thesis, Laboratory for Computer Science, Massachusetts Institute of Technology, 1987.

No context found.

T.-A. Chu. Synthesis of self-timed VLSI circuits from graph-theoretic specifications. PhD thesis, MIT, June 1987.

No context found.

T.-A. Chu, \Synthesis of Self-Timed VLSI Circuits from GraphTheoretic Speci cations", PhD thesis, MIT Laboratory for Computer Science, Jun. 1987.

No context found.

T.-A. Chu, "Synthesis of Self-Timed VLSI Circuits from GraphTheoretic Specifications," Ph.D. Thesis, Department of Electrical Engineering and Computer Science, MIT, Cambridge, Massachusetts, USA, 1987.

No context found.

T.-A. Chu. Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications. PhD thesis, MIT Laboratory for Computer Science, June 1987.

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