M. Moudgill, K. Pingali, and S. Vassiliadis. Register renaming and dynamic speculation: an alternative approach. In Proceedings of MICRO-26, 1993.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....Restricting the resizing in this manner simplifies the circuitry [4] Before resizing, we must ensure the head and tail pointers do not straddle the partition to be disabled otherwise buffered instructions could be caught in the disabled partition. 4. 2 Register Rename Operation Register renaming [11, 17, 10, 15] performs logical (architectural) to physical register mappings, thereby eliminating write after read and write after write dependence when there are sufficient physical registers. In a processor such as IBM s Power4 which can support up to 200 instructions in flight through the pipeline ....

....are sufficient physical registers. In a processor such as IBM s Power4 which can support up to 200 instructions in flight through the pipeline simultaneously [15] register renaming is critical for exploiting the processor s superscalar capabilities. The approach to register renaming proposed by [11] utilizes the pool of registers more efficiently than alternative designs that maintain a separate pool of architected registers in addition to a register set for renaming. Without a separate pool of architected registers, before buffer resizing can occur all active registers in the partition to ....

Mayan Moudgill and Keshav Pingali and Stamatis Vassiliadis. Register renaming and dynamic speculation: an alternative approach. In Proceedings of MICRO-26, pages 202--213, March 1993.

....maintained in a separate bank (perhaps in the ROB) Since a functional unit could source values in either bank, this partitioning into two banks does not result in a reduction in access time. The conditions under which a register can be deallocated have been dealt with in detail by Moudgill et al. [18]. Wallace and Bagherzadeh [27] and Monreal et al. [17] propose delaying the allocation of registers until the time to actually write the value, thereby improving its utilization. Partitioned non hierarchical register file organizations have been proposed in the past [1, 4, 5, 8, 12, 15, 21] These ....

M. Moudgill, K. Pingali, and S. Vassiliadis. Register Renaming and Dynamic Speculation: an Alternative Approach. In Proceedings of MICRO-26, 1993.

....that supersedes the register be older than oldest(US ; UB ) typical uniprocessor) or oldest(UL ; US ; UB ) multiprocessor or other multiple master system) In our implementation, we augment every physical register with a Superseded bit and a Pending count. This support is similar to [17]. The Superseded bit marks whether the instruction that supersedes the register is older than oldest(US ; UB ) or oldest(UL ; US ; UB ) in multiprocessors) which implies that so are all consumers. The Pending count records how many instructions among the consumers and producer of this register ....

....in order until the excepting instruction is met. Smith and Pleszkun [18] discuss several methods to support precise exceptions. The Reorder Buffer (ROB) and the History Buffer are presented, among other techniques. The second category includes work related to register recycling. Moudgill et al. [17] discuss performing early register recycling in out of order processors that support precise exceptions. However, the implementation of precise exceptions in [17] relies on either checkpoint rollback for every replay event, or a history buffer that restricts register recycling to only the ....

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M. Moudgill, K. Pingali, and S. Vassiliadis. Register renaming and dynamic speculation: An alternative approach. In International Symposium on Microarchitecture, pages 202--213, Austin, TX, December 1993.

....requirements. A clustering organization proposed by Canal et al. [4] also partitions the register le, but makes copies of values depending on whether a cluster is going to need it or not. The conditions under which a register can be deallocated have been dealt with in detail by Moudgill et al. [15] in the context of register renaming. The speci c conditions under which we decide to copy a value from the L1 to the L2 have also been proposed by them in the context of a processor with imprecise exceptions. We describe a hardware mechanism to use these conditions in order to automate the ....

M. Moudgill, K. Pingali, and S. Vassiliadis. Register Renaming and Dynamic Speculation: an Alternative Approach. In Proceedings of MICRO, 1993.

....restoring the content of the corresponding checkpoint. A more cost effective scheme was derived and introduced in [Butl90] Other studies in the late 80s and in the 90s dealt with dependency tracking and renaming techniques. Only implementation details and few improvements were discussed, as in [Moud93][Fark95] A significant change is the virtual register renaming scheme [Gonz98] where the renaming is decoupled from the dependency tracking hardware and processed right before the write back stage. Memory renamers traditionally feature a reorder buffer like structure called a forwarding buffer ....

M. Moudgill, K. Pingali, and S. Vassiliadis, "Register Renaming and Dynamic Speculation: an Alternative Approach", in Proceedings of the 26 th Annual International Symposium on Microarchitecture, Austin, TX, December 1993, pp.202-213.

....etc. 73 Register renaming is implemented in several different ways in commercial microprocessors. These designs are surveyed in detail elsewhere [Sima00] but we describe them briefly here. One mechanism is called the merged register file, used in the MIPS R10000 and Alpha 21264 processors [Moud93, Yeag96]. In this design, the architected state and rename state are mingled in a single large register file which we will call the physical register file. Both speculative and non speculative state share the same storage structure in this design. The register renaming and register release mechanisms must ....

....that value 1. We use the notation NPR and NLR throughout the remainder of this chapter. 74 have a copy of it; 3) the physical register has been unmapped, i.e. the value has been superseded by later architected state. These conditions were enumerated in essentially the same form in earlier work [Moud93] and forms the basis of the MIPS R10000 microarchitecture [Yeag96] One way to ensure these conditions are met is to allow a physical register P to be freed and reclaimed when the logical register L that it maps has been written by a later instruction which has also been committed to architected ....

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M. Moudgill, K. Pingali and S. Vassiliadis. Register Renaming and Dynamic Speculation: An Alternative Approach. Proc. 26th Intl. Symp. Microarchitecture (MICRO'93), pp. 202-213, Dec. 1993.

....with the banks having different speeds. While this degrades IPC, it enables a faster clock. Other work [17, 34] proposes improving register utilization by allocating registers when instructions complete. The relaxed conditions for releasing registers into the free list have been proposed before [18] in the context of processors with imprecise exceptions. The primary advantage of the future thread is its prefetching effect. A number of hardware [6, 13, 26] and software prefetching [16, 19] schemes have been proposed. Most of these schemes can do a better job of prefetching as they exploit ....

M. Moudgill, K. Pingali, and S. Vassiliadis. Register Renaming and Dynamic Speculation: an Alternative Approach. In Proceedings of MICRO, 1993.

....queue to be issued or being executed in its corresponding functional unit) It has been committed as well as all the instructions that used the produced value but the next instruction with the same logical destination register has not been committed yet. As described by other authors (Moudgill, Pingali Vassiliadis, 1993; Smith Sohi, 1995) the second source of register waste can be eliminated by associating a counter with each physical register that keeps track of the pending read operations. A register is freed whenever the counter is zero, provided that the corresponding logical register has been ....

M. Moudgill, K. Pingali and S. Vassiliadis (1993). Register Renaming and Dynamic Speculation: an Alternative Approach. In Proc. of Int. Symp. on Microarchitecture, pp. 202-213.

....map tables, that record a pointer to the most recent rename of each architected register in a single direct mapped table. The Intel Pentium Pro [7] IBM RIOS [2] HP PA8000 [9] and MIPS R10000 [5] all use map tables. Map table designs have also been investigated in the research community [8][10]. There are two common ways to implement renaming with a map table. The Pentium Pro and HP parts store the rename registers separate from the architected registers in a combined RRF and reorder buffer (ROB) while the IBM RIOS and MIPS R10000 store the rename registers and the architected ....

M. Moudgill, K. Pingali, and S. Vassiliadis. Register Renaming and Dynamic Speculation: an Alternative Approach. In Proceedings of the 26th Annual International Symposium on Microarchitecture, pages 202-213, December 1993.

....by Springer Verlag in their series on Lecture Notes in Computer Science. The following publications acknowledge support from one or both of the NSF grants listed above, and are listed in reverse chronological order. This list omits a few papers Pingali wishes he had not published [9] 58] 68] [96], 84] 66] 59] 52] 65] 67] 56] 10] 55] 7.2.2 Development of Human Resources During the current funding period, the following graduate students received doctoral degrees: Anne Rogers (assistant professor, Princeton University) Micah Beck (assistant professor, University of ....

A. M. Rogers and K. Pingali. Register renaming and dynamic speculation: an alternative approach. IEEE Transactions on Parallel and Distributed Systems, 5(3):281--298, March 1994.

....in their series on Lecture Notes in Computer Science. The following publications acknowledge support from one or both of the NSF grants listed above, and are listed in reverse chronological order. This list omits a few papers Pingali wishes he had not published [9] 58] 68] 96] [84], 66] 59] 52] 65] 67] 56] 10] 55] 7.2.2 Development of Human Resources During the current funding period, the following graduate students received doctoral degrees: Anne Rogers (assistant professor, Princeton University) Micah Beck (assistant professor, University of Tennessee ....

M. Moudgill, K. Pingali, and S. Vassiliadis. Register renaming and dynamic speculation: an alternative approach. In Proceedings of the 26th International Symposium on Microarchitecture (MICRO 26), pages 202--213, Austin, TX, December 1993.

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M. Moudgill, K. Pingali, and S. Vassiliadis. Register renaming and dynamic speculation: an alternative approach. In Proceedings of MICRO-26, 1993.

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M. Moudgill, K. Pingali, and S. Vassiliadis. Register renaming and dynamic speculation: An alternative approach. In Intl. Symp. on Microarchitecture, Dec. 1993

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M. Moudgill, K. Pingali, and S. Vassiliadis. Register renaming and dynamic speculation: an alternative approach. In Proceedings of the 26th International Symposium on Microarchitecture, pages 202--213, December 1993.

No context found.

M. Moudgill, K. Pingali, and S. Vassiliadis. Register Renaming and Dynamic Speculation: An Alternative Approach. In International Symposium on Microarchitecture, pages 202--213, Austin, Texas, December 1993.

No context found.

M. Moudgill, K. Pingali, and S. Vassiliadis. Register renaming and dynamic speculation: An alternative approach. In Proc. of the 26th International Symposium on Microarchitecture, pages 202--213, December 1993.

No context found.

M. Moudgill, K. Pingali, and S. Vassiliadis. Register renaming and dynamic speculation: an alternative approach. In Proceedings of the 26th International Symposium on Microarchitecture, pages 202--213, December 1993.

No context found.

M. Moudgill, K. Pingali, and S.Vassiliadis. Register renaming and Dynamic Speculation: an Alternative Approach. In Proceedings of the 26th International Symposium on Microarchitecture, December 1993.

No context found.

M. Moudgill, K. Pingali, and S. Vassiliadis. Register renaming and dynamic speculation: an alternative approach. 26th Annual International Symposium on Microarchitecture, December 1993.

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