J. Gong, D. D. Gajski, and S. Narayan, "Software Estimation Using A Generic-Processor Model", Proc. Europ. Des. & Test Conf, 1995, pp. 498-502.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....the final synchronous hardware description. SpecCharts [3] is another system specification language for hardware software codesign. The researchers have developed estimators for both software and hardware. Their software estimator is based on a generic processor model method of estimation [4]. Their hardware estimators can estimate based on many models such as a pin model, an area model, and a performance model [10] Through the use of a graphical interface and graphical representations of their estimations, hardware software codesign can be done in an interactive environment. 2.2. ....

....or VHDL is executed, we can compute the average probability for branches and the number of iterations for loops. 3.2.2. The software estimator The method of software estimation we are proposing is a hybrid of both the established processor specific estimator and the generic processor estimator. [4] Figure 5 illustrates our method of software estimation. We propose the use of processor specific compilers with Specification Metrics instructions GCC Compiler with processor specific flag set Processor specific TBI generator 68000 instruction set timing and size information GCC ....

J. Gong, D. Gajski, and S. Narayan. Software estimation using a generic-processor model. European Design & Test Conference, pages 498--502, March 1995.

....relatively to a given workload, which is determined by the specified applied software system. So, among software characteristics it is desirable to have some metrics concerning the performancedetermining properties of software application domain (AD) However, as follows from literature analysis [Gong95], there are no software metrics which could be used to make accurate predictions concerning behavioral characteristics of software from the point of view of speed up of software reused or migrated on the TS. The point is that, no suitable mathematical models to express the relationships between ....

.... either of the major system resources (and the amount overlap in CPU and I O utilization) or other times for the separate events in the system ( e.g. duration of primitive operations of some high level language [Saavedra89] Thereby, in spite of different performance providing problem definitions[Saavedra89, Gong95, Edward96 ], the sums of products of program operations frequencies values and expected (or measured) times of their execution on the TS are used as a performance metric. As an immediate effect of the lack of the model, the possible increasing of the CS design cost may be pointed out, because optimization ....

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J. Gong et al, Software Estimation Using of Generic-Processor Model, Proc. of EDAC95, 1995.

....the semantics of the underlying processor description language cannot easily be used to describe other hardware components such as hardware accelerators. An example of software modeling at a higher level of abstraction, thus more suitable for performance estimation, is the approach presented in [6, 7]. In this model, instructions are modeled as three operand generic instructions. This approach is sufficiently abstract to be used in target architecture evaluation. However, this technique is also guided towards micro processor descriptions. Hardware components like accelerators, co processor, ....

J. Gong, D. D. Gajski, and S. Narayan. Software Estimation Using a Generic-Processor Model. In European Design and Test Conference, 1995.

....our main distinction in this section will be made between non preemptive static cyclic scheduling and preemptive fixed priority scheduling. We have to mention that performance estimation and scheduling of processes typically requires, as an input, estimated execution times of single processes [Eng99, Ern97, Gon95, Hen95, Li95, Lun99, Mal97, Suz96]. Non preemptive static cyclic scheduling. Static cyclic scheduling of a set of data dependent software processes on a multiprocessor architecture has been intensively researched [Kop97a, Xu00] Several approaches are based on list scheduling heuristics using different priority criteria [Cof72, ....

J. Gong, D. D. Gajski, S. Narayan, "Software Estimation Using A Generic-Processor Model", Proceedings of the European Design and Test Conf, 498-502, 1995.

....estimation must be extremely fast. Online estimation is the focus of Section 4. Pre estimation is a hard problem, requiring a combination of profilers, estimators, and synthesis tools, but is beyond the scope of this paper. Discussions regarding estimation techniques and accuracies can be found in [5, 17]. For a discussion on a more complex method for hardware size estimation, which considers hardware sharing among functional objects, see [18] 3 Kernighan Lin heuristic background An improvement heuristic is one that, given an initial partition, moves nodes among parts seeking a lower cost ....

J. Gong, D. Gajski, and S. Narayan, "Software estimation using a generic processor model," in Proceedings of the European Design and Test Conference (EDTC), pp. 498--502, 1995.

....each behavior and variable object with internal computation time (ict) weights for each possible component, corresponding to a variable s access time, or to a behavior s execution time excluding communication time. Times can be obtained with the aid of profiling and static estimation techniques [11]. We also annotate each edge with access frequency weights, which can also be obtained through profiling. Furthermore, we associate a bits weight with each edge, representing the number of bits sent during each transfer. For 88 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. ....

....I O pins and gates, and by a technology file describing an RT component library. A standard processor is characterized by a maximum program memory size, a bus size, a maximum bus bitrate, and a technology file describing how to map a generic instruction set to the processor s instruction set [11]. A memory is characterized by the number of ports, number of words, word width, and access time. A bus is characterized by the number of wires, protocol, and maximum bit rates. Ideally, we would also be able to allocate special purpose processor components (e.g. DMA controllers) as well as ....

[Article contains additional citation context not shown here]

J. Gong, D. Gajski, and S. Narayan, "Software estimation using a generic processor model," in Proc. European Design Test Conf. (EDTC), 1995, pp. 498--502.

....each behavior and variable object with internal computation time (ict) weights for each possible component, corresponding to a variable s access time, or to a behavior s execution time excluding communication time. Times can be obtained with the aid of profiling and static estimation techniques [11]. We also annotate each edge with access frequency weights, which can also be obtained through profiling. Furthermore, we associate a bits weight with each edge, representing the number of bits sent during each transfer. For each annotations, we might associate average, minimum and maximum values. ....

....I O pins and gates, and by a technology file describing an RT component library. A standard processor is characterized by a maximum program memory size, a bus size, a maximum bus bitrate, and a technology file describing how to map a generic instruction set to the processor s instruction set [11]. A memory is characterized by the number of ports, number of words, word width, and access time. A bus is characterized by the number of wires, protocol, and maximum bitrates. Ideally, we would also be able to allocate special purpose processor components (e.g. DMA controllers) as well as ....

[Article contains additional citation context not shown here]

J. Gong, D. Gajski, and S. Narayan, "Software estimation using a generic processor model," in Proceedings of the European Design and Test Conference (EDTC), pp. 498--502, 1995.

.... c5:accfreq (c5:tt Centroid:et) in1val:et = in1val:ict 0 in2val:et = in2val:ict 0 EvalRule:et = EvalRule:ict c8:accfreq (c8:tt trunc:et) 3) Pre estimation A behavior s internal computation time can be computed during pre estimation through profiling and scheduling [15]. Profiling determines the execution count of each basic block. A schedule for each basic block is then estimated for each possible processor component, using compilation for standard processors and synthesis for custom processors. The summation over all blocks of each block s execution count ....

....each generic instruction would require in each processor, the estimator computes the software size. A target processor s technology file can be developed based on the size information of the processor s instruction set. Details on derivation of technology files for specific processors are given in [15]. Some experiments comparing the generic model with the processorspecific model yielded inaccuracy of roughly 7 [15] Note that the same generic processor approach would be applied for software performance estimation. Specifically, the technology file of the target processor would include not ....

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J. Gong, D. Gajski, and S. Narayan, "Software estimation using a generic processor model," in Proceedings of the European Design and Test Conference (EDTC), pp. 498--502, 1995.

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J. Gong, D. D. Gajski, and S. Narayan, "Software Estimation Using A Generic-Processor Model", Proc. Europ. Des. & Test Conf, 1995, pp. 498-502.

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