A. Seznec, "Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio," Proc. 21st Ann. Int'l Symp. Computer Architecture, pp. 384-393, 1994.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....they are either all in the cache, or none of them are in the cache. In contrast, for a line of decoded instructions, some of them may be in the DFC and the rest may be not in the DFC because of cacheable classification. In order to share a tag among these instructions, we use sectored cache design [9] for the DFC. A sectored cache consists of several sectors and each sector is made up of several lines. The sector format is shown in Figure 2. All the lines in a sector share one tag and each line has its own valid bit. One disadvantage of sectored cache design is possible cache underutilization ....

A. Seznec. Decoupled sectored caches: conciliating low tag implementation cost. In Int'l Symp. Computer Architecture, pages 384--393, 1994.

....[I] or the number of sets [19] JETTY may easily co exist with such optimizations and will still be valuable especially when the application requires use of all L2 cache resources. Techniques that reduce tag array sizes (e.g. CAT [27] Seznec s tag indirection [23] and sectored tags [22]) can help reduce tag lookup power dissipation. While these techniques reduce the tag array size they also place restrictions on the block address distribution. Moreover, these techniques may impact L2 access latency. 6 Conclusion In this work, we were motivated by the increasing importance of ....

A. Seznec. Decoupled sectored caches: Conciliating low tag implementation cost and low miss ratio. in Proc. 21st Annual Intl. Symposium on Computer Arehitecture, Apr. 1994.

.... consumption in computing systems [23] Much of this attention has focused on architectural and circuit techniques for reducing on chip processor power and energy consumption via techniques such as clock gating [2] memory subsystem storage structure optimizations [3] 5] 16] 17] 21] 14] 24] 25][26][27] 30] system bus optimizations [8] 12] pipeline speculation gating [19] and main memory access [18] Recently, a study by Moshovos et al. examined the potential for ltering remote snoop requests by checking them against a small Jetty table to avoid tag lookups and reduce on chip power ....

A. Seznec. Decoupled sectored caches: Conciliating low tag implementation cost and low miss ratio. In Proc. 21st Annual Intl. Symposium on Computer Architecture, April 1994.

....Table 4 9: Policy efficiencies; 1MB 4 way set associative L2, threshold and bound = 2 96 ular cache. The performance penalty of the subblocked cache may be reduced by mechanisms that allow data to be mapped into the cache at a finer granularity. One possible solution is the decoupled sector cache [103], which associates multiple tags with each block. In Chapter 5, we propose a different solution, which maps data into the cache at a subblock granularity, but uses block sized tags to keep track of the data. 4.5 Bus prioritization Speculative loading of subblocks (as determined by DSF and SBP) ....

....Dual Footprint Bus prefetching 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4. 0 su2cor hydro2d mgrid applu turb3d apsi IPC Figure 4 4: Performance of traffic optimization schemes 100 Another alternative to mitigating the mapping granularity problem would be to implement a decoupled sector cache [103], associating multiple tags with each block. The decoupled subblocked cache has the potential to work synergistically with the proposed policies, improving performance above and beyond that attainable with a fixed block size. In the next section, however, we propose a different solution to ....

Andr Seznec. Decoupled Sectored Caches: conciliating low tag implementation cost and low miss ratio. In Proceedings of the 21st Annual International Symposium on Computer Architecture, pages 384--393, April 1994.

....lines within the sector. Although this approach would benefit from reduced bandwidth requirements, the unused cache lines within the sectors would result in poor utilization of the cache, resulting in worse hit ratios and, ultimately, worse cache performance. We use a decoupled sectored cache [15] (described in Section 6.2) that allows us to use smaller arrays with little impact on the cache access latency. 3. Experimental Setup We study Spatial Footprint Prediction for L1 data caches. In the base configuration, the L1 data cache used is a 16 Kbyte four way set associative cache. Each ....

....by caches with small lines. In a sectored cache, a single address tag is associated with a sector consisting of several cache lines, while validity tags are associated with each of the cache lines. However, this results in bad performance due to poor utilization of the cache resources. Seznec [15] proposed decoupled sectored caches as a way to reconcile low tag implementation cost with low miss ratio. In a decoupled sectored cache, instead of the static association between the tag and data, the association is determined dynamically at allocation time. The address tag location associated ....

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A. Seznec. Decoupled sectored caches: Conciliating low tag implementation cost and low miss ratio. In Proceedings of the 21st Annual International Symposium on Computer Architecture, pages 384--393, Chicago, IL, April, 1994.

....cache, several consecutive memory blocks are grouped together to form a sector in the cache that share a same tag. While sectored cache can reduce the tag cost, it generally shows higher miss ratio than nonsectored caches. Seznec has proposed an interesting technique called decoupled sector cache [18], which not only reduces tag cost, but also improves the performance of sectored cache. While Seznec s work aims at decoupling the tags from data in a sector of a sectored cache, the objective of our work is to exploit the locality property of addresses of memory references. In order to achieve ....

A. Seznec, "Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio," Proc. 21st Ann. Int'l Symp. Computer Architectures, pp. 384-393, Apr. 1994.

....with di erent forms of hardware prefetching [8, 12] Bypassing and selective caching has also been successfully investigated [9] Sectored caches [10] attempt to reduce the fraction of useless words fetched by splitting cache lines in smaller sublines and only fetching necessary sublines. Seznec [17] also proposed Decoupled Sectored Caches, an original implementation of sectored caches that combines reduced memory tra c with low miss ratio by allowing several sublines to reside in di erent cache locations. However, few sophisticated techniques to improve spatial and temporal locality ....

Andre Seznec. Decoupled sectored caches: Conciliating low tag implementation cost and low miss ratio. In Proceedings of the 21th International Symposium on Computer Architecture, pages 384-393, 1994.

....tag 1 . The size of the tag array in a sectored cache is significantly lower than the size of the tag array in a non sectored cache. Unfortunately, on many applications, a sectored cache exhibits significantly higher miss ratios than a non sectored cache. The aim of the decoupled sectored cache [8] is to conciliate low tag implementation cost and low miss ratio. In a traditional sectored cache, each cache line location is statically linked to one and only one address tag location. In the decoupled sectored cache, this monolithic association is broken; the address tag location associated ....

....of the tag array and the data array are equal. On a (N; P ) decoupled sectored cache, these two arrays are more independent; the usual associative organizations (directmapped, set associative, fully associative) might be considered independently for these two arrays. These cases are detailed in [8]. We illustrate here the tag checking in the general case where the address tag array and the data array are both set associative. To simplify figures and notations, the offset in the cache blocks will not be represented in the remainder of the paper. Let us divide the address C of a memory ....

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A. Seznec, "Decoupled Sectored Caches: conciliating low tag implementation cost and low miss ratio", Proceedings of the 21st International Symposium on Computer Architecture, April 1994

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A. Seznec, "Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio," Proc. 21st Ann. Int'l Symp. Computer Architecture, pp. 384-393, 1994.

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Andr'e Seznec. Decoupled Sectored Caches: conciliating low tag implementation cost and low miss ratio. Proc. 21st Annual International Symposium on Computer Architecture, pp. 384--393, Chicago, IL, April 18--21 1994.

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Andre Seznec. Decoupled Sectored Caches: conciliating low tag implementation cost and low miss ratio. In Proc. 21st Annual International Symposium on Computer Architecture, pages 384-393, Chicago, IL, April 18-21 1994.

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Andr'e Seznec. Decoupled Sectored Caches: conciliating low tag implementation cost and low miss ratio. Proc. 21st Annual International Symposium on Computer Architecture, pp. 384--393, Chicago, IL, April 18--21 1994.

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A. Seznec, 'Decoupled sectored caches: conciliating low tag implementation cost', Inten. Symp. on Computer Architecture, pp. 384-393, 1994.

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A. Seznec, "Decoupled sectored caches: conciliating low tag implementation cost and low miss ratio," In Proceedings of the 21st Annual Intl. Symposium on Computer Architecture, April 1994.

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A. Seznec, "Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio," Proc. 21st Ann. Int'l Symp. Computer Architecture, ACM, 1994, pp. 384-393.

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