P. Rossmanith. The owner concept for PRAMs. In Proc. of 8th Symposium on Theoretical Aspects of Computer Science, number 480 in Lecture Notes in Computer Science, pages 172--183. Springer, 1991.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....it is not reasonable to assume that communication (such as derivation) takes only one step. We can also think of PCGSTT as modelling data independence features by way of grammar systems, a notion well studied in the parallel complexity community under the name of owner read, owner write PRAM (see [23, 24, 34]) Observe that data independence is a particularly useful and reasonable assumption when considering both derivation steps and communication steps of a grammar system to happen in unit time steps since, then, a possibly long communicated terminal string can be safely bu ered somewhere, and the ....

P. Rossmanith. The owner concept for PRAMs. In 8th Annual Symposium on Theoretical Aspects of Computer Science STACS'91, volume 480 of LNCS, pages 172-183. Springer, 1991.

....be difficult, since the usual restrictions of a pushdown store (e.g. the one turn property, or using a counter instead of a push down) all collapse to logspace. Here, parallel machine models seem helpful, leading to two intermediate classes: the parallel pointer machine [7, 16] and the OROW PRAM [23]. As a consequence of our main result we get OROW algorithms for the elements of RUSPACE(logn) taking time O(log 2 n= log log n) We are also able to show that all sets in RUSPACE(logn) are accepted in logarithmic time on a parallel pointer machine. This latter containment is somewhat ....

....[10] CROW PRAMs need only logarithmic time to recognize any given language in DSPACE(logn) There are two important ways to restrict CROW PRAMs and still maintain this property. One way is to restrict the concurrent read access to the global memory, which leads to the OROW PRAMs of Rossmanith [23]. The other way is to restrict the arithmetical capabilities of the instruction set leading to rCROW PRAMs and to parallel pointer machines [7, 16] 3 Unambiguity A concept intermediate in power between determinism and nondeterminism is Unambiguity. A nondeterministic machine is said to be ....

[Article contains additional citation context not shown here]

P. Rossmanith. The owner concept for PRAMs. In Proc. of the 8th STACS, number 480 in LNCS, pages 172--183. Springer, 1991.

.... PRAM s with a polynomial number of processors by XRYW TIME (f (n) For XRYW TIME(log k n) we use the abbreviation XRYW k . We know the relationships (for k 1) CRCW k = AC k [59] NC k OROW k CROW k SAC k [54; 64] CROW 1 = LOGDCFL [24] and DSPACE(logn) OROW 1 [54]: In CRCW PRAM s, global memory behaves like a shared memory, since each processor can access each cell of global memory. In the most restricted model, the OROWPRAM, however, the global memory is deteriorated to a set of one directional channels between pairs of processors. Thus an OROW PRAM is ....

....: P [P [i] Both the control structure and the write structure of this algorithm are data independent. On the other hand, we use the inputs S[i] and P [i] as index values, i.e. addresses, and thus the read structure is data dependent. b) Another possibility is to use Rossmanith s OROW algorithm [54]. Its underlying idea is that now Q S i and Q P i execute log n times the statements S[P [i] S[i] resp. P [S[i] P [i] Here both the control structure and the read structure are data independent, whereas the write structure is data dependent. We solved the pointer jumping problem either ....

[Article contains additional citation context not shown here]

P. Rossmanith. The owner concept for PRAMs. In C. Choffrut and M. Jantzen, editors, Proceedings of the 8th Symposium on Theoretical Aspects of Computer Science, number 480 in Lecture Notes in Computer Science, pages 172--183, Hamburg, Federal Republic of Germany, Feb. 1991. Springer.

....LOG(DCFL) CROW TIPR(log; pol) Dymond and Ruzzo [6] 4. P = CROW TIPR(log n; expol) Lange and Rossmanith [13] 5. CROW TIME(log k n) SAC k for k 1. 6. DAuxPDA TISP i c log k n ; log n j = CROW TIPR i log k n; pol j for k 1. 7. NC = CROW TIPR(polylog; pol) By Rossmanith [18], we know NC k OROW TIME(log k n) 8. DAuxPDA TISP i pol; log k n j = CROW TIPR i log n; c log k n j for k 1. 9. CROW TIPR(log f ; g) DTISP Gamma f O(1) log g; log g log f Delta : 10. DAuxPDA TISP i pol; 2 log k j SC k 1 for k 1. 11. SC = CROW TIPR(log; ....

P. Rossmanith. The owner concept for PRAMs. In Proc. of the 8th STACS, number 480 in LNCS, pages 172--183. Springer, 1991.

.... memory concept in PRAMs has appeared following a preliminary version of this paper [12] Fich and Wigderson give a lower bound separating EROW and CROW PRAMs [14] Rossmanith introduces and studies Owner Read, Owner Write PRAMs, showing, for example, that they can do list ranking in O(log n) time [31]. Nishimura considers the owner concept in CRCW PRAMs [29] Niedermeier and Rossmanith [27, 26] have considered the owner concept with other PRAM variants. Lin, et al. show that CROW PRAMs are sufficiently powerful to execute a variant of Cole s parallel merge sort algorithm in time O(log n) ....

P. Rossmanith. The owner concept for PRAMs. In C. Choffrut and M. Jantzen, editors, STACS 91: 8th Annual Symposium on Theoretical Aspects of Computer Science, volume 480 of Lecture Notes in Computer Science, pages 172--183, Hamburg, Germany, Feb. 1991. Springer-Verlag.

....PRAMs, a processor is associated with each cell, and only this processor can read the cell s contents. In an owner read owner write (OROW) PRAM, the processor owning a cell for writing is in general di#erent from the processor owning the same cell for reading. For more details, see [DR86, Ros91, FLR96] We also analyze the bit complexity of our algorithm, and show an implementation in Boolean NC 2 . The goal is to sum up the contribution of all clow sequences at the output 6.1 2 gate of the circuit. The output gate is a sum, over all 1 # k # n, of C k , where C k is the sum of ....

P. Rossmanith. The owner concept for PRAMs. In<F4.621e+05> Proceedings of the 8th Symposium on Theoretical Aspects of Computer Science,<F5.291e+05> STACS, volume 480 of<F4.621e+05> Lecture Notes in Computer<F5.291e+05> Science, pages 172--183, Berlin, 1991. Springer.

....be difficult, since the usual restrictions of a pushdown store (e.g. the one turn property, or using a counter instead of a push down) all collapse to logspace. Here, parallel machine models seem helpful, leading to two intermediate classes: the parallel pointer machine [6,14] and the OROW PRAM [20]. As a consequence of our main result we get OROW algorithms for the elements of StUSPACE(logn) taking time O(log 2 n= log log n) We are also able to show that all sets in StUSPACE(logn) are accepted in logarithmic time on a parallel pointer machine. This latter containment is somewhat ....

....[9] CROW PRAMs need only logarithmic time to recognize any given language in DSPACE(logn) There are two important ways to restrict CROW PRAMs and still maintain this property. One way is to restrict the concurrent read access to the global memory, which leads to the OROW PRAMs of Rossmanith [20]. The other way is to restrict the arithmetical capabilities of the instruction set leading to rCROW PRAMs and to parallel pointer machines [6,14] 3 Unambiguity A concept intermediate in power between determinism and nondeterminism is Unambiguity. A nondeterministic machine is said to be ....

[Article contains additional citation context not shown here]

P. Rossmanith. The owner concept for PRAMs. In Proc. of the 8th STACS, number 480 in LNCS, pages 172--183. Springer, 1991.

.... memory concept in PRAMs has appeared following a preliminary version of this paper [13] Fich and Wigderson give a lower bound separating EROW and CROW PRAMs [15] Rossmanith introduces and studies Owner Read, Owner Write PRAMs, showing, for example, that they can do list ranking in O(log n) time [31]. Nishimura considers the owner concept in CRCW PRAMs [29] Niedermeier and Rossmanith [27, 26] have considered the owner concept with other PRAM variants. Lin, et al. show that CROW PRAMs are sufficiently powerful to execute a variant of Cole s parallel merge sort algorithm in time O(log n) ....

P. Rossmanith. The owner concept for PRAMs. In C. Choffrut and M. Jantzen, editors, STACS 91: 8th Annual Symposium on Theoretical Aspects of Computer Science, volume 480 of Lecture Notes in Computer Science, pages 172--183, Hamburg, Germany, Feb. 1991. Springer-Verlag.

....following submodels. Arbitrary ( 64] If two or more processors write into a memory location in a given step, then one of the values is selected arbitrarily to become the new value. Nothing is known about the selection. 10 Other memory access models for PRAMs has also been proposed. See e.g. [37, 59]. Tolerant ( 25] The contents of a memory location does not change, if two or more processors try to write into that location in a given step. Common ( 63] If two or more processors attempt to write into a given memory location in a given step, then they must be attempting to write the same ....

P. Rossmanith. The Owner Concept for PRAMs. In Proceedings, 8th Annual Symposium of Theoretical Aspects of Computer Science, STACS 91, Lecture Notes in Computer Science 480, pages 172--193, 1991.

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P. Rossmanith. The owner concept for PRAMs. In Proc. of 8th Symposium on Theoretical Aspects of Computer Science, number 480 in Lecture Notes in Computer Science, pages 172--183. Springer, 1991.

....of CREW PRAMs [DR86] In CROW PRAMs each memory cell is mapped to one processor, its owner. Only this special processor is allowed to write into this memory cell. Analogously to this owner write PRAM, also a owner read restriction can be defined which leads to OROW PRAMs that were investigated in [Ros91]. In OROW PRAMs each memory cell has a write owner and a (possibly different) read owner. Only the write owner is allowed to write into and only the read owner is allowed to read from a memory cell. We will use a definition of PRAMs similar to [SV84] Each PRAM has an unbounded global memory and ....

....only if the value is 0. The simulating PRAM is clearly exclusive write since AND gates receive at most one 0 and OR gates at most one 1. It is also owner read. Each memory cell has two read owners due to fan out two of the circuit, but this can be easy changed to only one read owner (see also [Ros91]) The more interesting part of the simulation is the handling of SELECT gates. Here again, we assign a memory cell to each output of the SELECT gate and, additionally, one to each input. There are two additional memory cells L and R. Memory cell L will contain the number of the input on the left ....

[Article contains additional citation context not shown here]

P. Rossmanith. The owner concept for PRAMs. In Proc. of 8th Symposium on Theoretical Aspects of Computer Science, number 480 in Lecture Notes in Computer Science, pages 172--183. Springer, 1991.

....access mechanisms to shared memory. We restrict ourselves to the two in this respect weakest and, thus, most promising models for an efficient direct realization, that is, we consider the EREW PRAM (exclusive read, exclusive write) 6, 7] and most of all the OROW PRAM (owner read, owner write) [11]. In OROW PRAM s each shared memory cell has a uniquely determined read owner processor and a uniquely determined write owner processor. These processors are the only ones allowed to read from and to write into a cell, respectively. Thus OROW PRAM s may be viewed as a parallel computer where ....

....tree (1 t h) Dymond and Ruzzo [3] introduced the owner concept for the write access in PRAM s, yielding a frequently occurring subclass of the CREW PRAM called CROW PRAM. Following this line, that idea was also applied with respect to the read access of a PRAM, resulting in the OROW PRAM model [11]. For an OROWPRAM (owner read, owner write) there exist functions write owner and read owner that map each cell of shared memory to a unique processor that is the only one allowed to write into the cell or to read from the cell, respectively. A cell may have a write owner distinct from its ....

[Article contains additional citation context not shown here]

P. Rossmanith. The owner concept for PRAMs. In C. Choffrut and M. Jantzen, editors, Proc. of 8th Symposium on Theoretical Aspects of Computer Science, number 480 in Lecture Notes in Computer Science, pages 172--183, Hamburg, Federal Republic of Germany, Feb. 1991. Springer.

....further demand concerning the input output convention. More precisely, the BRAM model, which is formally introduced in Section 3, evolves informally speaking by putting together the concept of data independent (or oblivious) computations [15] with the owner read, owner write restriction for PRAM s [17]. In addition, we assume that each of the p processors of a BRAM holds n data items of an input of total size pn in its local memory and that the number of global memory cells may range from p to p 2 . Note that, for example, BRAM s with global memory size O(p) in essence model bounded degree ....

....processor numbers differ by one. The most restricted PRAM variant with respect to access possibilities to shared memory is the owner mechanism introduced by Dymond and Ruzzo [7] Later on, OROW PRAM s (Owner read, Owner write) were introduced as a still more restricted variation of EREW PRAM s [17]. Here, a uniquely determined read owner, resp. write owner, processor is assigned to each global memory cell. The read owner is the only processor with read and the write owner is the only processor with write permission for this cell. More formally, there are functions called write owner(i; n) ....

P. Rossmanith. The Owner Concept for PRAMs. In C. Choffrut and M. Jantzen, editors, Proc. of 8th STACS, number 480 in LNCS, pages 172--183, Hamburg, Federal Republic of Germany, Feb. 1991. Springer-Verlag.

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