M. C. McFarland, A. C. Parker, and R. Camposano, "Tutorial on highlevel synthesis," presented at the Design Automation Conf., 1988.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....After all, it is often reported that the bottleneck in software debugging is compilation time. D. Software versus Hardware Compilation The analogy between hardware and software compilation has been known and exploited for a long time [16] Hardware compilation (or high level synthesis) 7] [27] involves functional and register allocation and scheduling, followed by component synthesis and optimization. Software compilation [1] traditionally involves register allocation and instruction selection, followed by local optimizations. Exploiting the link between these two continues to be a ....

M. C. McFarland, A. C. Parker, and R. Camposano, "Tutorial on highlevel synthesis," in Proc. 25th ACM/IEEE Design Automation Conf., Anaheim, CA, 12--15 June 1988, pp. 330--336.

....an abstract description of the behavior of the part. Many different hardware designs can implement a given behavioral description, a subset of which also meet specified requirements such as cost, performance, and testability. Current research in hardware synthesis techniques (e.g. Brayton 87] McFarland 88] De Micheli 94] typically focuses on the use of minimum area or maximum performance as the primary criteria for selecting the best hardware implementation. Some synthesis for testability techniques attempt to generate the lowest cost, highest performance implementation that also meets certain ....

McFarland, M. C., A. C. Parker, and R. Camposano, "Tutorial on High-Level Synthesis," 25th ACM/IEEE Des. Autom. Conf., Anaheim, CA, USA, pp. 330-336, June 12-15, 1988.

....technology) or allow the user to specify those characteristics. Many different hardware designs can implement a given behavioral description, a subset of which also meet specified requirements such as cost, performance, and testability. Existing hardware synthesis systems (see [Brayton 87] McFarland 88] De Micheli 94] typically use cost and performance as the main criteria for selecting the best hardware implementation, and seldom even consider test issues during the synthesis process. We have developed and implemented a computer aided design tool, named Odin, whose primary objective is to ....

McFarland, M. C., A. C. Parker, and R. Camposano, "Tutorial on High-Level Synthesis," 25th ACM/IEEE Design Automation Conference, Anaheim, CA, pp. 330-336, June 12-15, 1988.

....abstract description of the behavior of the design. Many different hardware designs can implement a given behavioral description, a subset of which also meet specified requirements such as area, performance, and testability. Current research in hardware synthesis techniques (e.g. Brayton 87] McFarland 88] De Micheli 94] typically focuses on the use of minimum area or maximum performance as the primary criteria for selecting the best hardware implementation. We have developed and implemented new synthesis for BIST techniques whose primary objective is to satisfy requirements associated with a ....

McFarland, M. C., A. C. Parker, and R. Camposano, "Tutorial on High-Level Synthesis," 25th ACM/IEEE Des. Autom. Conf., Anaheim, CA, USA, pp. 330-336, June 1215, 1988.

....is associated with a corresponding weight gain. The local solution is optimal for the given set of operations in the sense that the summation of the weights of the matching generated for those operations is maximum. This distinguishes our algorithm from other heuristics such as list scheduling [24, 19, 23], force directed scheduling [25, 9] etc. which generally make a scheduling decision about a single operation at a time. In our algorithm we generate a solution for a collection of operations while maximizing the scheduling objective for this set of operations. While the quality guarantee remains ....

....a control step with no violation of data dependency. Considering one control step at a time, operations are selected from this ordered list one by one according to some priority function and scheduled at the control step under consideration. There exist a variety of realizations of this approach [19], 30] 18] 24] 23] 16] In force directed scheduling [26] the goal is to create a balanced distribution of operations among control steps. Using the mobility of each operation to define possible intervals of execution, potential demand for each control step is determined. The ....

M. C. McFarland, A. C. Parker, and R Camposano. Tutorial on high-level synthesis, July 1988. Design Automation Conference.

....has been based on the synchronous data flow model of computation. As pointed out earlier, most high level synthesis systems for DSP, video, and other numerically intensive applications either assume that all input and delay node samples are available at the same time (all phases are zero) [33], 34] 40] or indirectly assign values to the phases by using schedulers that incorporate techniques such as overlapped scheduling and software pipelining to generate complex time shapes [12] 25] 38] However, only recently has some limited work been done on relaxing the assumption that all ....

M. C. McFarland, A. C. Parker, and R. Camposano, "Tutorial on highlevel synthesis," in Proc. 25th Design Automation Conf., 1988, pp. 330--336.

....by jointly designing both hardware and software components of an embedded system architecture. This state of the art methodology is an elegant two dimensional extention of the onedimensional High Level Synthesis (HLS) methodology [40] which has gained vast acceptance in both industry and academia [17, 68, 99]. Three processes are identified in the embedded system design flow [32, 71] 1. Modelling 2. Validation 3. Synthesis These processes are fundamental steps in any methodology aimed to design an embedded system. In addition, correctness identification and estimation are intermediate steps ....

M. C. McFarland, A. C. Parker, and R. Camposano. Tutorial on high-level synthesis. Design Automation Conference (DAC), pages 330--336, Anaheim, USA, 1988.

....self and predecessor successor forces. The total force on an operation is simply the sum of these forces. Both minimum latency and minimum resource problems could be solved using force directed techniques. This methodology was first proposed by [27] It has been used and in systems like HAL [74]. Other Scheduling Techniques: Scheduling is a very well studied and understood problem with many solutions and methodologies. Path based scheduling is another interesting algorithm which addresses the scheduling of control flow graphs [80] Trace driven scheduling and percolation scheduling have ....

M.C. McFarland, A.C. Parker and R. Camposano. " Tutorial on High Level Synthesis ". In Design Automation Conference, pages 330--336, June 1988.

....thesis. 2 Fundamentals of High Level Synthesis The task of synthesis process is to take the specifications of the behavior required for a system and a set of constraints and goals to be satisfied, and to find a structure that implements the behavior while satisfying the goals and constraints [1, 2]. The behavior of the system refers to the ways the system or its component interact with their environment (mapping from inputs to outputs) The structure refers to the set of interconnected components that constitute the system (described by a netlist) Usually there are many different ....

....Since digital circuits are designed at several levels of abstraction, synthesis can take place at various levels of abstraction as shown in Fig.1. High level synthesis is a transformation from an algorithm level specification of the behavior of a system to a register transfer level specification [1, 2, 12, 13]. The number of reasons of being high level synthesis popular are the followings [1, 2] Shorter design cycle: If more of design process is automated faster products can be made available at cheaper price. Fewer errors: Since the synthesis process can be verfied easily chances of error is less ....

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M.C.McFarland, et. al., "Tutorial on High-Level Synthesis" Proc. of the 25th A CM/IEEE Design Automation Conference, 1988, pp.330-336.

....latches. Up to 22 reduction in the circuit area and up to 73 reduction in the power consumption have been achieved. 1. Introduction Research in high level synthesis (HLS) has drawn a lot of attention because of its potential in significantly increasing the productivity of VLSI design [7] 8][12]. Experience has shown that HLS tools have better chance to be accepted in such specific application domains as digital signal processing (DSP) circuits [15] and control dominated circuits [6] 18] Control dominated circuits are used in a wide variety of applications including protocol converters, ....

M. C. McFarland, A. C. Parker, and R. Camposano, "Tutorial on High-Level Synthesis," 25th ACM/IEEE Design Automation Conference, pp. 330-336, 1988.

....scheduling problem has also been shown to be NP hard. Key Words: Scheduling, NP complete problems, High Level Synthesis 1 Introduction The problem of scheduling is an important one in the automation of VLSI design. It is a primary problem in high level synthesis (HLS) of VLSI systems [1]. The scheduling problem surfaces soon after the behavioural specifications have been converted to the intermediate form [2] which is usually in the form of a set of data flow graphs. These may be in the form of directed acyclic graphs (DAGs) which contain the dependencies between the operations. ....

M. C. McFarland, A. C. Parker, and R. Camposano, "Tutorial on high-level synthesis, " in Proceedings of the 25th ACM/IEEE Design Automation Conference, 1988.

....lower bound estimation 1. Introduction In high level synthesis, a behavioral description which specifies the sequence of operations to be performed is transformed into a register transfer structure that implements the behavior. One of the main tasks in high level synthesis is scheduling [1, 2]. In scheduling process, each operation is assigned to one control step (shortly cstep) that is, a clock cycle during which it will be executed, while the precedence relations between operations and the timing and or area constraints are preserved. Within a control step, a separate FU (Functional ....

....data flow graph when the total number of csteps is 3, and Figure 2 illustrates how the lower bound on the number of FUs of each type and that on the total FU cost are estimated for the example in Figure 1. For example, two multiplications 1 and 2 are guaranteed to be executed in cstep interval [1, 2], since their ASAP and ALAP csteps are included in this interval respectively. So d2=2e = 1 is estimated as a candidate of the lower bound on the number of multipliers. Such the candidates are estimated over all the cstep intervals as shown in Figure 2. In this case, the estimated lower bound on ....

M. C. McFarland, A. C. Parker and R. Composano, "Tutorial on High-Level Synthesis," Proc. 25th DAC, pp.330-336, June 1988.

....over their entire scope of visibility and relative to all the other carriers in the entire specification. This approach is quite expensive in computer time and memory, as it involves determining the maximal compatibility classes among a large number of carriers, a process known to be NP complete [2, 19]. On the other hand, the proposed algorithm achieves nearly the same effect of global optimization without using explicit inline expansion. The compatibility between all possible pairs of carriers in the entire specification is not evaluated and hence gain in both memory and time. Experimental ....

....words, the description language does not influence the optimization algorithm. The description has a main( a function namely, gcd( and a procedure namely rem( 3 Scheduling Assumptions We assume that the register optimization phase follows the scheduling phase during high level synthesis [12, 13, 19]. The job of the scheduler is to assign a control step to each statement in a module, relative to the first statement in the module. Schedulers attempt to generate minimal length schedules subject to the given user specified constraints such as area, clock speed and available resources. In the ....

M. C. McFarland, A. Parker, and R. Camposano, "Tutorial on High-Level Synthesis," 25th Design Automation Conference, pp. 401-439, June 1988.

....synthesis and hierarchical package design. We provide detailed partitioning algorithms and experimental results. 1 Introduction High level synthesis converts a behavioral specification of a digital system into an equivalent rtl design that meets a set of stated performance constraints [1, 2, 3]. This rtl design can be partitioned into multiple segments to realize a multichip design. Partitioning rtl designs, however, has various drawbacks: 1) Control lines could be crossing segment boundaries; 2) Operators could be shared by operands in different segments, this results in poor ....

M.C. McFarland, A.C. Parker, and R. Camposano, "Tutorial on High-Level Synthesis," Proc. 25th Design Automation Conference, pp. 330--336, June 1988.

....After all, it is often reported that the bottleneck in software debugging is compilation time. Software versus Hardware Compilation The analogy between hardware and software compilation has been known and exploited for a long time [Gaj88] Hardware compilation (or high level synthesis) BCP92b, MPC88] involves functional and register allocation and scheduling, followed by component synthesis and optimization. Software compilation [ASU88] traditionally involves register allocation and instruction selection, followed by local optimizations. Exploiting the link between these two continues to be ....

M.C. McFarland, A.C. Parker, and R. Camposano. Tutorial on high-level synthesis. In Proceedings of the 25th ACM/IEEE Design Automation Conference, Anaheim, CA, USA, 12-15 June 1988, pages 330-6. IEEE New York, NY, 1988. 40

....Transfer) Level 1 of abstraction. Here the emphasis of CAD and DA tools is on synthesizing a design in terms of ALUs, registers, multiplexors, and a control sequence table, given a behavioral description of the hardware to be designed. An excellent tutorial to ongoing work at this level is [5]. As the field of Functional Block Level design automation matures, it is appropriate to begin developing tools for higher levels of design. At the next higher level, the Algorithmic Level (also known as the Behavioral Level) it is appropriate to explore behavioral and structural partitioning. It ....

M.C. McFarland, A.C. Parker, and R. Camposano. Tutorial on High Level Synthesis. In Proc. of the 25th DAC, pages 330--336. ACM/IEEE, Anaheim, California, June, 1988.

....implementation language is enriched by loop invariants. If those are given prior to the synthesis process and the underlying data types are only Booleans, i.e. finite length bitvectors, then the complete synthesis and verification process runs automatically. 1 Introduction As high level synthesis [1] has reached the stage of industrial applications, it has turned out that the implicit assumption, that the generated structures just implement the behavioral specification, does not always hold. Software faults, inevitable in complex design tools, hinder the use of synthesized hardware, ....

M.C. McFarland, A.C. Parker, and R. Camposano. Tutorial on high-level synthesis. In 25th Design Automation Conference, pages 330--336, 1988.

....Given an algorithm, they are based upon its behavioral description and generate a data path netlist and a control graph. Generation of the FSM (Finite State Machine) controlling the data path is then performed by using the relationship data path control according to some optimization criteria ([6]) But this double description does compromise their flexibility, that is to say their ability to accept a few changes in the algorithm specifications without redesigning the whole architecture. Moreover, global optimization of the desired architecture is not possible due to the lack of a unified ....

Michael C. McFarland, A.C. Parker, and Raul Camposano. Tutorial on high-level synthesis. In Proceedings of 25th ACM/IEEE Design Automation Conference, 1988.

.... system is to generate a design solution that satisfies a set of resource budgets (typically for TIME and AREA) and maximizes the value of the solution as determined by an objective function (typically AREA3TIME n for some n) A more detailed description of high level synthesis can be found in [2]. 1.2 Interactions We will now discuss the kinds of interactions that occur in this task. Although the details are specific to High Level Synthesis, we believe the general categories apply to many other problems. 1.2.1 Resource Interactions Reasoning with resource goals is difficult because the ....

M. C. McFarland S.J., A. C. Parker, and R. Camposano, "Tutorial on high-level synthesis," in Proceedings of the 25th Design Automation Conference, 1988.

....widely accepted means for validating circuit correctness. However, since exhaustive simulation is not feasible for large designs, design error freeness cannot be ensured. Automated high level synthesis is another means to derive presumably correct circuit implementations from a given specification [1]. However since the synthesis programs are themselves complex and do not have an underlying formal apparatus, the correctness of the circuits generated cannot be guaranteed. Furthermore, they are restricted to certain classes of circuits (e.g. signal processors) and are still inferior to manually ....

M.C. McFarland, A.C. Parker, and R. Camposano. Tutorial on high-level synthesis. In 25th Design Automation Conference, pages 330--336, 1988.

....are two types of resource sharing. The first one is sharing functional units such as arithmetic unit, buses etc. This type of problem has been extensively studied and successfully applied to an area of design automation. It is called scheduling and allocation in high level synthesis literature [16, 17]. The main techniques used to solve the problem are control and data flow analysis. The second kind of resource sharing is complicated components such as memory or registers. Since these components have their own internal structures, flow analysis alone is insufficient to achieve the goal. In our ....

....r 1 ; 2. rd(M dcr2(a s) and saved to some register r 2 ; REFERENCES 15 3. rd(M a i) and saved to some register r 3 ; 4. wr(arith(r 3 r 1 r 2 ) M dcr2(a s) This transformation, called serialization, is analogous to the problems of allocation and scheduling in high level synthesis (e.g. [16, 17]) register allocation and code generation in compiler design (e.g [20] and microcode generation (e.g. 21] 9] gives a formalization of the serialization problem in the current algebraic framework. Unfortunately, it is readily proved that the serialization problem is unsolvable in general [9] ....

McFarland, M. C., Parker, A. C., and Camposano, R. Tutorial on high-level synthesis. In Proceedings of the 25th ACM/IEEE Design Automation Conference (Anaheim, CA, 1988), ACM/SIGDA, pp. 330--336.

....Synthesis Raul Camposano Synopsys, Inc. Mountain View, CA 94043 Extended Abstract Since the 1988 tutorial on behavioral (high level) synthesis which appeared in the DAC [1] proceedings (and later in the proceedings of the IEEE [2] much has happened in the field. Behavioral synthesis is now considered mainstream EDA as evidenced by the number of articles at conferences, journals and books. May be even more significant, several products are being offered ....

M.C. McFarland, A.C. Parker, R. Camposano, Tutorial on High-Level Synthesis, Proc. 25th Design Automation Conference, pp.330-336, June 1988,California

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M. C. McFarland, A. C. Parker, and R. Camposano, "Tutorial on highlevel synthesis," presented at the Design Automation Conf., 1988.

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McFarland, M. C., Parker, A. C. and Camposano, R., Tutorial on High-Level Synthesis, Proc. 25th ACM/IEEE Design Automation Conference, 1988

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M.C. McFarland, A.C. Parker, R. Camposano: "Tutorial on High-Level Synthesis", 25th Design Automation Conference, pp. 330-336, 1988.

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