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P. Paulin and J. Knight. Force-Directed Scheduling for the Behavioral Synthesis of ASICs. IEEE TCAD, 8(6):661--678, June 1989.

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An Efficient and Versatile Scheduling Algorithm - Based On Sdc   (Correct)

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P. Paulin and J. Knight. Force-Directed Scheduling for the Behavioral Synthesis of ASICs. IEEE TCAD, 8(6):661--678, June 1989.


Architecture and Synthesis for On-Chip - Multicycle Communication Jason   (Correct)

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P. Paulin and J. Knight, "Force-directed scheduling for behavioral synthesis of ASICs," IEEE Trans. Computer-Aided Design, vol. 8, pp. 661--679, Jun. 1989.


Behavioral Level Guidance Using Property-Based Design.. - Lisa Marie Guerra (1996)   (1 citation)  (Correct)

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P. Paulin and J. Knight, "Force-directed scheduling for the behavioral synthesis of ASIC's," IEEE Transactions on CAD, Vol. 8, No. 6, pp. 661-679, 1989.


Information Theoretic Measures for Power Analysis - Diana Marculescu Radu (1996)   (31 citations)  (Correct)

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P. Paulin, and J. Knight, `Force-directed Scheduling for the Behavioral Synthesis of ASICs', IEEE Transactions on CAD, vol. CAD-8, No. 6, pp. 661-679, July 1989. 24 List of figures and tables captions:


Timing Analysis in High-Level Synthesis - Andreas Kuehlmann Reinaldo (1992)   (5 citations)  (Correct)

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P. G. Paulin and J. P. Knight, "Force-directed scheduling for the behavioral synthesis of ASIC's," IEEE Transactions on Computer-Aided Design, vol. CAD-8, pp. 661--679, June 1989.


Engineering Change Protocols for Behavioral and System.. - Kirovski, Drinic.. (2005)   (Correct)

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P. Paulin and J. Knight, "Force-directed scheduling for the behavioral synthesis of ASICs," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 8, no. 6, pp. 661--679, Jun. 1989.


Multiple Behavior Module Synthesis - Based On Selective   (Correct)

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P.G. Paulin and J.P. Knight, "Force-Directed Scheduling for the Behavioral Synthesis of ASIC's," IEEE Transactions on Computer-Aided Design, vol. 8, pp. 661-678, June 1989.


A Behavioral Synthesis System for Asynchronous Circuits - Sacker, Brown, Rushton.. (2004)   (Correct)

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P. G. Paulin and J. P. Knight, "Force-directed scheduling for the behavioral synthesis of ASIC's," IEEE Trans. Computer-Aided Design, vol. 8, pp. 661--679, June, 1989.


F. Dartu and L. Pileggi, "Calculating worse-case gate.. - Ebeling And Lockyear   (Correct)

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P. Paulin and J. Knight, "Force-directed scheduling for the behavioral synthesis of ASIC's," IEEE Trans. Computer-Aided Design, vol. 8, pp. 661--679, June 1989.


Adapting Static Single Assignment for Hardware Compilation - Ryan Kastner Elaheh   (Correct)

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P. Paulin and J. Knight, "Force-Directed Scheduling for the Behavioral Synthesis of ASIC's", IEEE Transactions on CAD/ICAS, vol. 8, no. 6, pp. 661-679, July 1989.


Unknown - Background We Measured   (Correct)

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P.G. Paulin and J.P. Knight, "Force-directed Scheduling for the Behavioral Synthesis of ASICs," IEEE Trans. on Computer-Aided Design, Vol. 8, No. 6, pp. 661-679, June 1989.


Software Technology - Unu Iist Report   (Correct)

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P. Paulin and J. Knight. Force-Directed Scheduling for Behavioral Synthesis of ASICs. IEEE Trans. on CAD, 8(6), pp661-679, 1989.


Architecture and Synthesis for On-Chip Multicycle.. - Cong, Fan, Han, Yang.. (2004)   (1 citation)  (Correct)

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P. Paulin and J. Knight, "Force-directed scheduling for behavioral synthesis of ASICs," IEEE Trans. Computer-Aided Design, vol. 8, pp. 661--679, Jun. 1989.


Implementation Issues about the Embedding of Existing .. - Eisenbiegler.. (1996)   (3 citations)  (Correct)

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Pierre G. Paulin and John P. Knight. Force-directed scheduling for the behavioral synthesis of asic's. IEEE Transactions on Computer Aided Design, 8(6):661--679, June 1989. This article was processed using the L A T E X macro package with LLNCS style


Unknown -   (Correct)

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P. Paulin, J. Knight, " Force Directed Scheduling for Behavioral Synthesis of ASICs", IEEE Transactions on CAD, 8(6): 661-679, 1989.


Energy and Transient Power Minimization during Behavioral Synthesis - Mohanty (2003)   (Correct)

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P. G. Paulin and J. P. Knight, "Force Directed Scheduling for the Behavioral Synthesis of ASICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, no. 6, pp. 661--679, June 1989.


Implementing Parallelism and Scheduling Data Flow Graphs on Java.. - Xu, Sha   (Correct)

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Paulin, P. & Knight, J.P. Force-directed Scheduling for the Behavioral Synthesis of ASIC's, IEEE Transactions on Computer-Aided Design 8,6, June 1989, 661-679.


Low Power Storage Cycle Budget Distribution Tool.. - Brockmeyer.. (2000)   (2 citations)  (Correct)

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P.Paulin, J.Knight, "Force-directed scheduling for the behavioral synthesis of ASIC's", IEEE Trans. on CAD, Vol.8, No.6, pp.661-679, June 1989.


On Computation and Resource Management in Networked .. - Ghiasi, Nguyen.. (2003)   (Correct)

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P. Paulin and J. Knight. "Force Directed Scheduling for Behavioral Synthesis of ASICs". In IEEE Transactions on CAD, volume 8, pages 661--679, 1989.


Unknown - An Efficient Representation   (Correct)

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P. G. Paulin and J. P. Knight. Force-directed scheduling for the behavioral synthesis of ASIC's. IEEE Transactions on Computer Aided Design, 8(6):661--679, June 1989.


Systematic Cycle Budget versus System Power.. - Brockmeyer.. (2000)   (2 citations)  (Correct)

No context found.

P.Paulin, J.Knight, "Force-directed scheduling for the behavioral synthesis of ASIC's", IEEE Transactions on Computer-Aided Design, Vol.8, No.6, pp.661-679, June 1989.


Low Power Storage for Hierarchical Graphs - Brockmeyer, Wuytack.. (2000)   (1 citation)  (Correct)

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P.Paulin, J.Knight, "Force-directed scheduling for the behavioral synthesis of ASIC's", IEEE Transactions on Computer-Aided Design, Vol.8, No.6, pp.661-679, June 1989.


A Layout Estimation Algorithm for RTL Datapaths - Nourani, Papachristou (1993)   (2 citations)  (Correct)

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P. Paulin and J. Knight, "Force-Directed Scheduling for the Behavioral Synthesis of ASIC's,"IEEE Trans. on CAD, June 1989.


On the Efficiency of Formal Synthesis - Experimental.. - Blumenrohr.. (1999)   (Correct)

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P. G. Paulin and J. P. Knight, "Force-directed scheduling for the behavioral synthesis of ASIC's," IEEE Transactions on Computer Aided Design, vol. 8, no. 6, pp. 661--679, June 1989.


Local Watermarking: Methodology and Application to.. - Kirovski, Potkonjak (2003)   (Correct)

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P. Paulin and J. Knight, "Force-directed scheduling for the behavioral synthesis of ASIC's," IEEE Trans. Computer-Aided Design, vol. 8, pp. 661--679, June 1989.

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