D. Thomas. Algorithmic and Register-transfer Level Synthesis. Kluwer Academic Publishers, 1990.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....to one or more memories in RTL implementations has been addressed extensively in previous work. Some HLS systems map arrays in the behavioral description into a single monolithic memory [6] 7] 8] 9] while others take the opposite approach by mapping each array to a separate memory [10]. In general, neither extreme is the optimal solution, necessitating the use of a many to many mapping scheme. Techniques to reduce memory size while mapping multiple arrays to a single memory under performance constraints are presented in [11] 12] Techniques for mapping multiple arrays to ....

D. Thomas, Algorithmic and Register-transfer Level Synthesis: The System Architect's Workbench, Kluwer Academic Publishers, Norwell MA, 1990.

....We report experimental results indicating the effectiveness of the proposed technique and summarize our ongoing work to further strengthen it. 1. Introduction High level synthesis (hls) systems generate register transfer level (rtl) designs from algorithmic behavioral specifications (Figure 1) [19, 15, 48, 8, 53, 26]. The rtl design consists of a data path and a controller. This paper is an extension to the work presented in the International Conference on Formal Methods in Computer Aided Design [29] Nov 1998. c fl 1999 Kluwer Academic Publishers. Printed in the Netherlands. The data path consists of ....

....proving to perform synthesis and verification hand in hand. McFarland [30] developed behavior expressions for abstract specification of behavior and described how such expressions can be used to examine the correctness of behavioral transformations used in the high level synthesis system SAW [48]. Aagaard and Leeser [1] reported a formally verified logic synthesis tool. Kropf et al. 27] presented a formal high level synthesis approach in which the target architecture, based on handshake processes, is produced using a few basic primitives. Proof obligations are automatically generated ....

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Thomas, D., E. Lagnese, R. Walker, J. Nestor, J. Rajan, and R. Blackburn: 1990, `Algorithmic and Register Transfer Level Synthesis: The System Architect's Workbench'. Kluwer Academic Publishers. 40

....step with no violation of data dependency. Considering one control step at a time, operations are selected from this ordered list one by one according to some priority function and scheduled at the control step under consideration. There exist a variety of realizations of this approach [19] [30], 18] 24] 23] 16] In force directed scheduling [26] the goal is to create a balanced distribution of operations among control steps. Using the mobility of each operation to define possible intervals of execution, potential demand for each control step is determined. The ....

D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, and R. L. Blackburn. Algorithmic and Register Transfer Level Synthesis: The System Architect's Workbench. Kluwer Academic Publishers, Norwell, MA, 1990.

....with Viewloglc Systems Inc. 293 Boston Post Road West, Marlboro, MA 01752. 1994 ACM 0 89791 685 9 94 0011 1. 50 552 for traditional sequential programming constructs, such as loops, variable assignments, and branches for which there are simple techniques to generate a control dataflow graph [2, 10, 11, 12, 13]. As a result, tools accept only extremely limited forms of waits and signals. For example, some tools restrict each process to a single read or write of a signM. Other tools treat signals as variables, which changes the functionality. Most do not differentiate properly between simple, bus, and ....

D. Thomas, E. Langese, R. Walker, J. Nestor, J. Ra- jan, and R. Blackburn, Algorithmic and RegisterTransfer Level Synthesis: The System Architect's Workbench. Kluwer Academic Publishers, 1990.

....Design Validation and Test Workshop (HLDVT 98) pp. 40 46, La Jolla, California, Nov. 12 14, 1998. 3] J. berg, P. Ellervee, A. Hemani, Grammar based Modelling of Clock Protocols for Low Power Implementation: A Case Study , In Proc. of NorChip 98, pp. 144 153, Lund, Sweden, Nov. 9 10, 1998. [4] A. Jantsch, J. berg, A. Hemani, Is there a Niche for a General Purpose Protocol Processor , In Proc. of NorChip 98, pp. 93 100, Lund, Sweden, Nov. 9 10, 1998. 5] A. Hemani, J. berg, A. Kumar Deb, D. Lindqvist, B. Fjellborg, System Level Prototyping of DSP ASICs using grammar based approach , ....

....be able to develop tools for design automation it is important to have conceptual models of the different domains and levels of descriptions if the designs we re trying to model. In 1983, Gajski and Kuhn introduced the Y chart for describing the taxonomy of design automation in electronic systems [3, 4]. It has proven to be a very valuable reference point and is up to today the most commonly used method for taxonomy of electronic systems. The Y chart is shown in Figure 1.1. Effort spent in developing a 20kGates design at various design steps over the years. Modified from [2] 40 60 70 30 50 ....

D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, R. L. Blackburn, "Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench", Kluwer Academic Publishers, Boston, 1990.

....1. Data ow graphs as in Sehwa [17] MAHA [18] HAL [19] and the Pangrle system [4] 2. High level languages, for example Pascal [20] Ada [21] 3. Enhanced versions of existing languages such as HandelC, HardwareC [22] or HardwarePal [23] 4. Hardware description languages such as ISPS [24], CADDY DSL [25] Verilog [26] or VHDL [27] Data ow diagrams may well be suitable for hardware independent, conceptual descriptions of a design, and notably are now a feature of the Ptolemy open modeling environment [28] It is unclear whether a data ow diagram is in a form suitable for direct ....

D. E. Thomas, E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, and R. L. Blackburn. Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench. Academic, Norwell, MA, 1990.

....to use Java [5] for this purpose. We utilized an adaptation of the JavaBeans model. JavaBeans make it possible to graphically model and visualize behavioral and structural aspects of hardware systems. 2 The Object Model Systems can be described from the viewpoints of structure and behavior [4, 21]. Using a suitable description language, it must be possible to describe the system from both viewpoints in a uniform manner. A mixed description should be applicable as well. The usual domains and its typical representatives are represented in g. 1. The de nition of the abstraction levels is ....

....a suitable description language, it must be possible to describe the system from both viewpoints in a uniform manner. A mixed description should be applicable as well. The usual domains and its typical representatives are represented in g. 1. The de nition of the abstraction levels is based on [21]. VHDL enables the description of behavabstraction level view System level Algorithmic level Register transfer level Logic level Electrical level Behavior Structure concurrent algorithms CPUs, memories ALUs,multiplexor,register algorithms boolean equations register transfers ....

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D.E. Thomas, E.D Lagnese, Walker R.A., J.A. Nestor, Rajan J.V., and Blackburn R.L. Algorithmic and Register-Transfer Level Synthesis: The System Architects Workbench. Kluwer Academic Publishers, 1991.

....techniques in high level synthesis systems are usually based on graph partitioning or coloring. Minimization algorithms for these graph techniques are known to be either NP hard [6, 10] or NP complete [14] However, polynomial time heuristics have been discovered for solving these problems [2, 8]. We will describe our verification approach in the context of one such popular heuristic based on compatibility graphs for carrier based register optimization. 5.1 Overview of the Clique Partitioning Algorithm for Register Allocation Tseng et al. used a polynomial time heuristic that constructs ....

....1 Lemma Introduction mergenodeswellformed.1. 1 : 1] sn = n 1 f 2g (N 1(sn) NOT (sn = sm) AND N 1(sm) 3] cs 1(sn) c1 1) OR cs 1(sm) c1 1) 4] cs 1(sn) c2 1) OR cs 1(sm) c2 1) 5] selectmatch(sn, N 1, E 1) sm [ 6] selectnode( N 1, E 1) cs 1, HP 1) sn [ 7] R 1(r 1) [ 8] r 1(c1 1) 9] r 1(c2 1) 1] N 1(sm) AND (cs 1(sm) c1 1) AND cs 1(sm) c2 1) 2] N 1(sn) AND (N 1(sm) AND (cs 1(sn) c1 1) AND (cs 1(sm) c2 1) AND (E 1(sn, sm) OR E 1(sm, sn) 3] N 1(sn) AND (cs 1(sn) c1 1) AND cs 1(sn) c2 1) 4] N 1(sm) AND (N 1(sn) AND ....

D.E. Thomas et al. "Algorithmic and Register Transfer Level Synthesis: The System Architect's Workbench". Kluwer Academic Publishers, 1990.

....processors (which have a single memory hierarchy) and can, therefore, use features like pointers and dynamic memory allocation. However, this approach is too restrictive for ASIC designs. On the other end of the spectrum, techniques that map each array to a separate memory have been proposed [11]. Many optimization and exploration techniques for memories in embedded systems have been addressed in [10] These include exposing the off chip memory architecture at the behavior level by introducing memory architecture specific access nodes in the behavioral description. Another contribution of ....

D. Thomas, Algorithmic and Register-transfer Level Synthesis: The System Architect's Workbench. Kluwer Academic Publishers, Norwell MA, 1990.

....from the MAIN module, padded with start and stop bits and shifted out serially (least significant bit first) on the TxD output at a rate determined by the baud rate setting in the mode word. 4. 5 Comparison With Existing Work Intel 8251 has been specified in HardwareC [25] and a variant of ISPS [42]. The specifications are available with the distribution of high level synthesis benchmarks. In this section we will compare the hopCP specification of the 8251 with its HardwareC and ISPS specifications. We will also touch 20 VENKATESH AKELLA, GANESH GOPALAKRISHNAN upon the drawbacks of ....

Thomas, D. E., Lagnese, E. D., Walker, R. A., Nestor, J. A., Rajan, J. V., and Blackburn, R. L. Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench. Kluwer Academic Publishers, Boston, 1990.

....to the way they conceive their work. However, each design must be described, eventually, at the lowest level (e.g. layout masks) in order to be fabricated. The transformation from one level of abstraction to the next is performed by various synthesis processes. High level or behavioral synthesis [11, 18, 19, 30, 31], is dened as the transformation of behavioral circuit descriptions into register transfer level (RTL) structural descriptions that implement the given behavior while satisfying user dened constraints. Today, with the adoption of standard Hardware Description Languages (HDLs) like VHDL [2, 3] or ....

D. E. Thomas, E. D. Lagnese, R.A. Walker, J. A. Nestor, J. V. Rajan, and R. L. Blackburn. Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench. Kluwer Academic Publishers, 1990.

....on a complete detailed representation of the logic. The most familiar and still quite widely used representation level is that of logic gates and latches, but computer designers increasingly use various kinds of automatic sythesis methods that elevate somewhat the level of logical description [14]. I will use the phrase gate level to mean the lowest level of description used by the logic designers, which should be the highest level that can convincingly be shown to be logically equivalent to the circuits actually fabricated. The hierarchical approach requires extra designer time, ....

....We would much prefer to have the ability to produce bug free designs to begin with, or to have formal proof methods capable of verifying big systems, or to have rigorous testing regimes that could certify correctness. We can certainly hope that the increasing use of logic synthesis techniques [14] will result in designs with fewer bugs. We can also hope that hardware verification methods of various kinds [2, 8] will be able to handle ever larger and more complex structures. But for the present, simulation is our lot, and we need to do it well. 16 ....

Thomas, D.E., et al. Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench. Boston, Kluwer Academic Publishers, 1990.

....and emphasis. The following are some of the hardware description formalisms currently in use: trace theory [19] CSP probe [34] Occam [7] used for the synthesis of pure asynchronous circuits, trace theory [18] for verification of asynchronous circuits, HardwareC [30] and ISPS (with variations) [57] for synthesis of synchronous circuits, functional calculus [26] for synthesis and verification of synchronous circuits, and Verilog HDL [54] and VHDL for modeling and simulation of synchronous and asynchronous circuits. It is difficult to place hopCP in this spectrum because it is an amalgamation ....

Thomas, D. E., Lagnese, E. D., Walker, R. A., Nestor, J. A., Rajan, J. V., and Blackburn, R. L. Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench. Kluwer Academic Publishers, Boston, 1990.

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D. E. Thomas, et al. Algorithmic and Register-Transfer Level Synthesis: the System Architect's Workbench, Kluwer Academic, 1990.

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D. Thomas. Algorithmic and Register-transfer Level Synthesis. Kluwer Academic Publishers, 1990.

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D.E. Thomas, E.D. Lagnese, R.A. Walker, J.A. Nestor, J.V. Rajan, B.L. Blackburn, "Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench", Kluwer Academic Publishers, 1990.

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Thomas D. E., Lagnese E. D., Walker R.A., Nestor J. A., Rajan J. V. and Blackburn R. L., "Algorithmic and RegisterTransfer Level Synthesis: The System Architect's Workbench", Kluwer Academic Publishers (1990).

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D. Thomas. Algorithmic and Register-transfer Level Synthesis. Kluwer Academic Publishers, 1990.

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D. Thomas, E. Lagnese, R. Walker, J. Nestor, J. Rajan, and R. Blackburn, Algorithmic and Register Transfer Level Synthesis: The System Architect's Workbench. New York: Kluwer, 1990.

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D.E. Thomas, E.D. Langnese, R.A. Walker, J.A. Nestor, J.V. Rajan, and R.L. Blackburn. Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench. Kluwer Academic Publishers, 1990.

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D.E. Thomas, E.D. Langnese, R.A. Walker, J.A. Nestor, J.V. Rajan, and R.L. Blackburn, Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench, Kluwer Academic Publishers, 1990.

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D.E. Thomas, E.D. Langnese, R.A. Walker, J.A. Nestor, J.V. Rajan, and R.L. Blackburn. Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench. Kluwer Academic Publishers, 1990.

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Thomas, et al., Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench, Kluwer Academic Publishers, 1990.

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D. E. Thomas et al., "Algorithmic and Register Transfer Level Synthesis: The System Architect's Workbench", Kluwer Academic Publishers, 1990.

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Thomas 90 D. E. Thomas, et al. Algorithmic and Register-Transfer Level Synthesis: the System Architect's Workbench, Kluwer Academic, 1990.

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