R. Brayton, et al. The Yorktown Silicon Compiler System. Silicon Compilation: pp. 204-310.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....movement by reducing the amount of compensation code required. Nonincremental moves of operations across large blocks of code are possible without visiting each intermediate node [47] Of course, several other representation models such as Value Trace (VT) 49] Yorktown Intermediate format (YIF) [50], Assignment Decision Diagrams (ADDs) 51] Hierarchical Conditional Dependency Graphs (HCDGs) 52] et cetera have been proposed earlier for high level synthesis. Also, Rim et al. 22] and Bergamaschi [53] have proposed new design representation models that attempt to bridge the gap between ....

R.K. Brayton, R. Camposano, G. De Micheli, R.H.J.M. Otten, and J. van Eijndhoven. The Yorktown Silicon Compiler System, chapter in Silicon Compilation. Addison-Wesley, 1988.

....that dependency constraints between operations are not violated. A number of different search strategies governing the application of transformations have been implemented and analysed. For example, whereas Expl [19] performs an exhaustive search of the design space, the Yorktown Silicon Compiler [29] uses heuristics to guide the order in which transformations are performed. The use of heuristics dramatically reduces the search space, allowing larger examples to be scheduled at the cost of possibly settling for a sub optimal solution. In contrast, constructive algorithms build up a schedule ....

....[89] choose to perform binding and allocation before scheduling. Each approach has its own advantages and shortcomings. A number of systems have tried to solve the phase order problem by combining scheduling, allocation and binding into a single phase. For example, the Yorktown Silicon Compiler [29] starts with a maximally parallel schedule where operations are all bound to separate resources. A series of transformations each of which affects the schedule, binding and allocation are applied in a single phase. Another approach is to formulate simultaneous scheduling and binding as an ....

BRAYTON, R., CAMPOSANO, R., MICHELI, G. D., OTTEN, R., AND VAN EIJNDHOVEN, J. The Yorktown Silicon Compiler System. Addison-Wesley, 1988.

....an operation to a resource can lead to the generation of additional steering logic and associated control logic. So, the cost models in compilers and synthesis tools for the various transformations have to be different. Previous work in HLS for microprocessor designs is limited. Brayton et al. [12] synthesized the 801 processor; a small processor with a simple data path, whereas Gupta et al. synthesized long latency functional units to embed into VLIW processors [13] Initialize(r1, r2) r2(i 1) Op2(i 1, r1(i 1) b) a) end loop r2(i) Op2(i, r1(i) Initialize(r1, ....

R.K. Brayton, R. Camposano, G. De Micheli, R.H.J.M. Otten, and J. van Eijndhoven. The Yorktown Silicon Compiler System, Silicon Compilation. Addison-Wesley, 1988.

....an operation to a resource can lead to the generation of additional steering logic and associated control logic. So, the cost models in compilers and synthesis tools for the various transformations have to be different. Previous work in HLS for microprocessor designs is limited. Brayton et al. [12] synthesized the 801 processor; a small processor with a simple data path, whereas Gupta et al. synthesized long latency functional units to embed into VLIW processors [13] Initialize(r1, r2) r2(i 1) Op2(i 1, r1(i 1) b) a) end loop r2(i) Op2(i, r1(i) Initialize(r1, ....

R.K. Brayton, R. Camposano, G. De Micheli, R.H.J.M. Otten, and J. van Eijndhoven. The Yorktown Silicon Compiler System, Silicon Compilation. Addison-Wesley, 1988.

....problem [1] For this reason, most high level synthesis system either separate the two tasks or use heuristic approaches. Some systems perform module binding before scheduling, e.g. Caddy DSL [2] and BUD [3] some systems perform scheduling before module binding, e.g. Facet [4] DAA [5] YSC [6], HIS [7] Combined heuristic scheduling and binding are performed in other synthesis systems, such as MAHA [8] ELF [9] Slicer Splicer [10] Chippe [11] Hal [12] and Genie S [13] It is important to remark that most of these approaches assume that each module is characterized a priori in terms ....

....by introducing sequencing dependencies between these operations. This is in contrast to heuristic approaches that combine scheduling with module binding [8, 10, 12] or perform module binding after scheduling [5, 4, 14] Several high level synthesis systems use variations of this general model [18, 6, 8, 2]. In particular, the Hercules Hebe high level synthesis system [17, 19] represents the hardware model by a polar hierarchical acyclic graph, where the vertices represent operations to perform and the edges represent the dependencies among the operations. The hierarchy supports procedure call, ....

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R. K. Brayton, R. Camposano, G. D. Micheli, R. Otten, and J. van Eijndhoven, "The Yorktown Silicon Compiler System," in Silicon Compilation (D. Gajski, ed.), Addison Wesley, 1988.

.... a gate level implementation that can be characterized as a purely hardware implementation (Figure 2) Recent strides in high level synthesis have made it possible to synthesize digital circuits from high level specifications and several such systems are available from industry and academia [1, 2, 3, 4, 5, 6, 7]. The outcome of synthesis is a gate level or geometric level description that is implemented as single or multiple chips. As the number of gates (or logic cells) increases such a solution requires use of semi custom or custom design technologies with associated increases in cost and design ....

....constraints are satisfied. 4 System synthesis From partitioned graph models, the next problem is to synthesize individual hardware and software components. Generation of hardware circuits from sequencing graph models has been addressed in detail elsewhere ( 18] and other approaches in [1, 2, 3, 5, 7]) So we concentrate on generation of software and interface circuitry from partitioned models. The problem of software synthesis is to generate a program from partitioned graph models that correctly implements the original system functionality. We assume that the resulting program is mapped to ....

[Article contains additional citation context not shown here]

R. K. Brayton, R. Camposano, G. D. Micheli, R. Otten, and J. van Eijndhoven, "The Yorktown Silicon Compiler System," in Silicon Compilation (D. Gajski, ed.), pp. 204--310, Addison Wesley, 1988.

....used for changing the implementation suggestion. 3. 2 Related work Several design systems for VLSI design based on the concept of transformational design exist or are under construction as part of larger projects (e.g. HYPER [20, 12, 21, 22] CAMAD [23, 24] SynGuide [25, 18] GATE [14] Yorktown [26], ESPRIT FORMAT[27] however most of them are restricted to optimizations at a single abstraction level (algebraic, loop, common subexpression elimination, retiming and scheduling transformations) some, such as GATE and HYPER, include limited refinement by means of strength reduction ....

R.K. Brayton, R. Camposano, G. DeMicheli, R.H.J.M. Otten, J.T.J. van Eijndhoven, The Yorktown Silicon Compiler System, eds. D. Gajski Addison-Wesley, 1988.

....with MASAI [FNS94] for automatic memory optimization for image processing algorithms. Other work that is (partially) transformation based includes the work on the Single Architectural Register Transfer model [Vem90] the System Architect s Workbench (SAW) Wat89] the Yorktown Silicon Compiler [BCD88, Cam89], and the Olympus tool set [MKM91] 4. Formalization of Behavior and Correctness Transformational design is a formal approach to design, in which most formal aspects are hidden from the designer. A formal framework for transformational design is necessary in order to prove the correctness of the ....

R.K. Brayton and R. Camposano and G. De Micheli and R.H.J.M. Otten and J.T.J. van Eijndhoven, The Yorktown Silicon Compiler System, eds. D. Gajski Addison-Wesley, 1988.

....by Kostelijk [KoW 93] It has been implemented in a CAD tool called RetLab as part of logic synthesis at PRL. A formal analysis of transformations used in Systems Architect Workbench (SAW) high level synthesis was studied by McFarland [McF 93] Transformations used in YIF (Yorktown Internal Form) YIF 88] have been proved to be behavior preserving [Cam 89] In this work, a strong notion of behavior equivalence based on an imperative semantics tied to a particular model of representation is used. A post facto verification method for comparing logic level designs against a restricted class of data ....

R.K. Brayton, R. Camposano, G. DeMicheli, R.H.J.M. Otten, and J.T.J. van Eijndhoven, The Yorktown Silicon Compiler System, Silicon Compilation, D. Gajski (Ed.), Addison-Wesley, 1988.

....Interactively used transformations on the control flow are discussed in [WaT89] In [MCF93] correctness of transformations in the System Architect s Workbench is investigated. Several errors were found, often related to incorrect use of bit array data types. The Yorktown Silicon Compiler based [BCD88] system [Cam89] emphasizes transformations to improve scheduling and allocation. The computations and control structure are not changed. The Yorktown Internal Form, which is similar to CDFG languages, is used as intermediate language. The transformation steps used for scheduling and allocation ....

.... of register transfer level transformations for scheduling and allocation has been dealt with in [Vem90] A formal analysis of transformations used in Systems Architect s Workbench (SAW) high level synthesis was studied by McFarland [McF93] Transformations used in YIF (Yorktown Internal Form) BCD88] have been proved to be behavior preserving [Cam89] In this work, a strong notion of behavior equivalence based on an imperative semantics tied to a particular model of representation is used. A post facto verification method for comparing logic level designs against a restricted class of ....

R.K. Brayton and R. Camposano and G. De Micheli and R.H.J.M. Otten and J.T.J. van Eijndhoven, The Yorktown Silicon Compiler System, eds. D. Gajski Addison-Wesley, 1988.

....of embedded systems. While considerable progress has been made in data oriented optimizations, control optimization has been fairly limited to those carried out by compilers at the register transfer level. In the past, variants of data flow graphs (DFGs) and control data flow graphs (CDFGs) [15, 16, 17, 18, 19, 20, 21] have been used for hardware synthesis and program compilation tasks. Most DFG based representations are quite efficient in implementing data oriented transformations, but the modeling of control flow is inadequate. In most CDFG models, control flow is often embedded in the modeling hierarchy that ....

R. K. Brayton, R. Camposano, G. D. Micheli, R. Otten, and J. van Eijndhoven, "The yorktown silicon compiler system," in Silicon Compilation (D. Gajski, ed.), pp. 204--310, Addison-Wesley, 1988. 56

....rapid prototyping. Last but not least, the MIM2SOLO environment is very user friendly. Both MIMOLA and SOLO 1400 offer interactive help facilities and on line documentation, and can be put to good use by inexperienced designers too. 2 Related Work High level synthesis systems, e.g. 10] 2] [1], 12] as a rule, transform the algorithmic system specification into a RT level structure with generic operators and the corresponding state transition tables. Early synthesis systems relied on manual transformation of this RT level description into a system built from TTL and MSI components. ....

....systems relied on manual transformation of this RT level description into a system built from TTL and MSI components. Most general silicon compilers use modulegenerators or datapath compilers, combined with logic optimization, to generate reasonable dense layouts from the RT level descriptions [1], 12] However, the modulegenerators usually introduce a severe technology dependence and interface badly with industrial standard environments. To ease acceptance of high level synthesis tools in industrial applications, it is crucial that the tools can be integrated with existing VLSI design ....

R. K. Brayton, et al., The Yorktown Silicon Compiler System, in D. Gajski, Silicon Compilation, Addison Wesley, 1988

....(textual) programs in high level programming languages. A program like description of hardware is compiled into a formal representation on which various synthesis tasks are carried out. Traditionally graph models such as variants of data flow graphs (DFGs) and control data flow graphs (CDFGs) [1, 2, 3, 4, 5, 6] have been used for various software compilation or hardware synthesis tasks. Most DFG based representations are efficient in implementing data oriented transformations, but often inadequate in control flow modeling. In most CDFG models, the control flow is embedded in the modeling hierarchy that ....

.... 1 before after condition user input optimization optimization to PUMPKIN gcd 272 230 positive inputs xi 0 yi 0; 15 motorcntrl 2952 366 no position variation iveer = 0; 88 motorcntrl 2952 2774 there is always variation iveer 0; 7 ecc 141 119 correct only single error rp[0] rp[1] rp[2] =1; 16 cp[0] cp[1] cp[2] 1; parker86 384 270 in2 in3 = 0 in2 in3 = 0; 29 traffic 35 34 no external dc specified 3 As shown in Table 4, use of external conditions can lead to reductions in the size of the hardware circuits. Thus HDL level presynthesis using PUMPKIN makes it possible to ....

[Article contains additional citation context not shown here]

R. K. Brayton, R. Camposano, G. D. Micheli, R. Otten, and J. van Eijndhoven, "The Yorktown Silicon Compiler System," in Silicon Compilation (D. Gajski, ed.), pp. 204--310, AddisonWesley, 1988.

....synthesis of digital systems consists of subtasks such as scheduling, resource allocation binding and control generation. Algorithms for these subtasks are developed for input description without exceptions. Consequently, high level synthesis systems such as ADAM [3] Olympus [4] SAW [5] and YSC [6], consider only structured inputs with very limited exception modeling such as RESET signals. The latter is incorporated in synthesized circuit by a specific choice of storage elements (flip flop with asynchronous set reset) In presence of control exception the input control flow is no longer ....

R. K. Brayton, R. Camposano, G. D. Micheli, R. Otten, and J. van Eijndhoven, "The Yorktown Silicon Compiler System," in Silicon Compilation (D. Gajski, ed.), pp. 204--310, Addison Wesley, 1988.

.... a gate level implementation that can be characterized as a purely hardware implementation (Figure 2) Recent strides in high level synthesis have made it possible to synthesize digital circuits from high level specifications and several such systems are available from industry and academia [1, 2, 3, 4, 5, 6, 7]. The outcome of synthesis is a gate level or geometric level description that is implemented as single or multiple chips. As the number of gates (or logic cells) increases such a solution requires use of semi custom or custom design technologies with associated increases in cost and design ....

....utilization constraints are satisfied. 4 System synthesis From partitioned graph models, the next problem is to synthesize individual hardware and software components. Generation of hardware circuits from sequencing graph models has been addressed in detail elsewhere ( 18] and other approaches in [1, 2, 3, 5, 7]) So we concentrate on generation of software and interface circuitry from partitioned models. The problem of software synthesis is to generate a program from partitioned graph models that correctly implements the original system functionality. We assume that the resulting program is mapped to ....

[Article contains additional citation context not shown here]

R. K. Brayton, R. Camposano, G. D. Micheli, R. Otten, and J. van Eijndhoven, "The Yorktown Silicon Compiler System," in Silicon Compilation (D. Gajski, ed.), pp. 204--310, Addison Wesley, 1988.

....12180 USA J. E. Mitchell is with the Department of Mathematics, Rensselaer Polytechnic Institute, Troy, NY 12180 USA IEEE Log Number 9405512 lutions, and exact algorithms, which find optimal solutions, have been used. A wide variety of heuristic algorithms are used, including the transformational [5], list [6] and forcedirected [7] scheduling heuristics. In contrast, most exact algorithms employ integer linear programming (ILP) to compute the optimal solutions. Although solving an ILP formulation is NP hard [3] significant progress has been made in the development of efficient ILP ....

R. K. Brayton, R. Camposano, G. De Micheli, and R.H.J.M Otten, "The Yorktown Silicon Compiler System", in Silicon Compilation, pp. 204--310. Addison-Wesley, 1988.

No context found.

R. K. Brayton, R. Camposano, G. DeMichelli, R. H. J. M. Otten, and J. T. J. van Eijndhoven, "The Yorktown silicon compiler system," in Silicon Compilation, D. Gajski, Ed. Reading, MA: Addison-Wesley, 1988.

....many timing and mapping restrictions which are not necessary, and severely limits the search space for optimal solutions of the generated architecture. A related approach is the introduction of sequence edges to denote the sequential ordering of operations as found in a (procedural) input language [Brayton88]. 2.3 Separation of data and control flow Many systems limit the data flow analysis to so called straight line code only, generating several blocks with data flow code [Lis88, Pangrle87] Conditional constructs, loops, and procedure calls are represented in a separate control graph. Although ....

BRAYTON, R.K., R. CAMPOSANO, G. DE MICHELI, R.H.J.M. OTTEN, AND J.T.J. VAN EIJNDHOVEN, "The Yorktown Silicon Compiler System," in Silicon Compilation , ed. D.D. Gajski, pp. 204--310, Addison--Wesley, 1988.

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R. Brayton, et al. The Yorktown Silicon Compiler System. Silicon Compilation: pp. 204-310.

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BRA88 Brayton, R. K. and Camposano, R. and De Micheli, G. and Otten, R. H. J. M. and van Eijndhoven, J. T. J. The Yorktown Silicon Compiler System. In Silicon Compilation. Gajski, D.D., Addison-Wesley, 1988.

No context found.

R.K. Brayton, R. Camposano, G. DeMicheli, R.H.J.M. Otten, and J.T.J. van Eijndhoven. The yorktown silicon compiler system. In D. Gajski, editor, The Yorktown Silicon Compiler System. AddisonWesley, 1988.

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