M. C. McFarland, A. C. Parker, and R. Camposano, "The high-level synthesis of digital systems," Proceedings of the IEEE, pp. 301--318, February 1990.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....The intermediate representation, which is kept in the compiler s data base, is accessible by the subsequent compilation phases. Well known intermediate representations for representing the algorithm include the static single assignment form (SSA form) 25] and the control dataflow graph (CDFG) [26], 27] In addition to the algorithmic specification, a retargetable compiler will also use a processor specification, that must be available in an internal model in the compiler s data base. This model may be generated automatically, starting from a processor specification language. Examples ....

M. C. McFarland, A. C. Parker, and R. Camposano, "The high level synthesis of digital systems," in Proc. IEEE, vol. 78, pp. 301--318. Feb. 1990.

....(operations, variables, assignments) are mapped to hardware units (components, registers, multiplexers, interconnection, busses) This step determines the complexity of the used hardware and also the performance of the resulting circuit. An overview on the state of the art is found in [McPC90] The data path synthesis can be roughly devided in the subtasks scheduling, allocation and assignment (also called binding) The scheduling assigns the operations to time steps and determines the performance of the circuit. The allocation determines the quantitiy of the hardware units and the ....

M. McFarland, A. C. Parker, R. Camposano, "The High Level Synthesis of Digital Systems", Proc. of the IEEE, Feb-1990

....is to improve the number of control steps of the circuit under fixed hardware resources. Keywords: high level synthesis, automatic scheduling 1. Introduction To reduce the development costs of integrated circuits it is necessary to use powerful CAD tools. With high level synthesis [CaRo89] [McPC90] the circuits behaviour can be specified at an abstract level by imperative programming language like descriptions. The data path as well as the controller is synthesized from this behavioural specification. This specification declares all operations and their control dependencies consisting of ....

M. C. McFarland, A. C. Parker, R. Camposano, "The High-Level Synthesis of Digital Systems", Proceedings of the 1EEE, Vol 78, 2-1990

....IEEE ASIC Conference and Exhibit (ASIC 94) pp 67 70, Rochester, New York, Sept. 1994. 10] A. Jantsch, P. Ellervee, J. berg, A. Hemani, H. Tenhunen, Hardware Software Partitioning and Minimizing Memory Interface Traffic , In Proc. of EURO DAC 94, pp 226 231, Grenoble, France, Sept. 1994. [11] P. Ellervee, J. berg, A. Jantsch, A. Hemani, Neural Network Based Estimator to Explore the Design Space at System Level , In Proc. of the 4th Biennial Baltic Electronic Conference, pp 391 396, Tallinn, Estonia, Oct. 1994. 12] J. Isoaho, J. berg, A. Hemani, H. Tenhunen, HLS based DSP ....

....This process is iterated until an acceptable solution is found. Such a methodology is termed specify explore refine methodology [15] Design space exploration is a complex task in general, but can be more manageable in a specific application domain 1.4. High Level Synthesis High Level Synthesis [10, 11, 12] is the task of translating a description of a design at the algorithmic level and translate it into a Register Transfer (RT) level description or an RT level netlist. Since most of the tool designers had been working with implementing DSP algorithms before the research started with HLS in the ....

M.C. McFarland, A.C. Parker, R. Camposano, "The High Level Synthesis of Digital Systems", In. Proc. of the IEEE, vol. 78, no. 2, pp. 301-318, Feb., 1990.

.... The complexity of modern digital circuits requires automated synthesis and optimisation techniques that can explore a wide class of implementations choices using computer aided design (CAD) tools [51] High level synthesis is the process of generating RTL structure from a behavioural description [129]. The modules (functional units) allocated by high level synthesis algorithms are generated by module generators which are able to synthesise the layout of modules with high performance and device density. The modules are placed in module libraries and have identical physical information. Given ....

M.C. McFarland, A.C. Parker, and R. Camposano. The high-level synthesis of digital systems. Proceedings of the IEEE, 78(2):301--318, February 1990.

....larger examples to be scheduled at the cost of possibly settling for a sub optimal solution. In contrast, constructive algorithms build up a schedule from scratch by incrementally adding operations. The simplest example of the constructive approach is As Soon As Possible (ASAP) scheduling [99]. This algorithm involves topologically sorting the operations in the dependency graph and inserting them (in their topological order) into time steps under the constraints that (i) Conventional HLS systems typically generate synchronous implementations. d) ASAP Schedule: 1 ....

....logic (e.g. multiplexers) required to connect resources. Let us start by considering the simplest case of minimising only the number of resources used (i.e. ignoring wiring and steering logic) In this case the standard technique involves building a compatibility graph from the input expression [99]. The compatibility graph has nodes for each operation in the expression and an undirected edge (n 1 , n 2 ) iff n 1 and n 2 can be computed on the same resource (i.e. if they do not occur in the same time step and there is a single resource type capable of performing the operations ....

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MCFARLAND, M., PARKER, A., AND CAMPOSANO, R. The high-level synthesis of digital systems. Proceedings of the IEEE 78, 2 (February 1990).

....Section V) during the application of transformations. II. PREVIOUS RELATED WORK Related work is outlined along two lines of research: highlevel synthesis techniques for testability and transformations. The mandatory tasks during high level synthesis are allocation, scheduling, and assignment [27], 39] all of which have been shown to have significant impact on the testability of the synthesized designs. Existing high level synthesis for testability techniques can be broadly classified according to the testing methodology targeted: BIST, gate level sequential ATPG, or hierarchical test ....

M. C. McFarland, A. C. Parker, and R. Camposano, "The high level synthesis of digital systems," Proc. IEEE, vol. 78, no. 2, pp. 301-317, 1990.

....that implement it. Finally, in section 5 we present experimental results. 2. RELATED RESEARCH Behavioral synthesis traditic.nally has been addressing synthesis and optimization of a single application for sampling rate, area, and more recently power and test hardware overhead minimization [8, 2]. Recently, a few efforts have been reported on behaviorel synthesis techniques for fault tolerant design. Karri and Orailoglu [6] presented scheduling, assignment and transformation based methods for fault tolerance against transient faults. Guerra et al. 41 presented the first work which ....

M.C. McFarland, A.C. Parker, R. Camposano, "The High-Level Synthesis of Digital Systems," Proc IEEE, Vol. 78, No. 2, pp. 301-317, 1990.

....is often very involved, time consuming, and cumbersome lRao90] Choosing the best fast DCT algorithm for a particular image or video application is a non trivial task. In such situations, behavioral synthesis tools provide an excellent option for rapid exploration of the algorithmic design space [Rab91, McF90]. After a long period of academic research, behavioral synthesis recently entered into a more mature phase where several research and commercial behavioral synthesis tools have become available, providing a reliable and fast path from functional specifi cation to custom ASIC implementation. In ....

M.C. McFarland, A.C. Parker, R. Camposano: "The High Level Synthesis of Digital Systems", Proc. of the IEEE, Vol. 78, No. 2, pp. 301-317, 1990.

....critical path delay) average energy savings in the range of to is obtained with respect to using a single frequency and single voltage scheme. 1 Introduction High level synthesis is the transformation from a behavioral specification of a system to its RTL structure specification [1]. The essential tasks involved in synthesis are scheduling, allocation, binding and clock selection. The need for low power synthesis is driven by several factors such as [6] 1) demand of portable systems (battery life) 2) thermal considerations (cooling and packaging) 3) environmental ....

M. C. McFarland, A. C. Parker, and R. Camposano, "The High-Level Synthesis of Digital Systems", Proc. of the IEEE, Vol.78, No.2, Feb 1990, pp.301-318.

....thesis. 2 Fundamentals of High Level Synthesis The task of synthesis process is to take the specifications of the behavior required for a system and a set of constraints and goals to be satisfied, and to find a structure that implements the behavior while satisfying the goals and constraints [1, 2]. The behavior of the system refers to the ways the system or its component interact with their environment (mapping from inputs to outputs) The structure refers to the set of interconnected components that constitute the system (described by a netlist) Usually there are many different ....

....Since digital circuits are designed at several levels of abstraction, synthesis can take place at various levels of abstraction as shown in Fig.1. High level synthesis is a transformation from an algorithm level specification of the behavior of a system to a register transfer level specification [1, 2, 12, 13]. The number of reasons of being high level synthesis popular are the followings [1, 2] Shorter design cycle: If more of design process is automated faster products can be made available at cheaper price. Fewer errors: Since the synthesis process can be verfied easily chances of error is less ....

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M.C.McFarland, et. al., "The High-Level Synthesis of Digital Systems", Proc. of the IEEE, Vol.78, No.2, Feb 1990, pp.301-318.

....) in order to minimize the estimated datapath area. The solutions generated by GLASS are superior to those obtained by existing graph theoretical P time techniques. 1. INTRODUCTION Behavioral synthesis aims at the generation of a structural description of a circuit from a behavioral description [1] by mapping high level objects (operations, variables) into register transfer components (functional, storage and interconnection units) Scheduling and allocation are two of the most important tasks in the synthesis of circuits from behavioral specifications. Scheduling distributes operation ....

M.C. McFarland, A.C. Parker, and R. Camposano. The High-Level Synthesis of Digital Systems. In Proc. of the IEEE, vol. 78, pages 201-318, Feb. 1990

.... A research area in the field of design automation of digital systems that is receiving increasing attention in the last years is high level synthesis (HLS) the mapping of a computation s behavioral description at the algorithmic level to a structural description at the register transfer level [5, 17]. In high level syn thesis, among other tasks, each operation in the behavioral description has to be scheduled at a specific time and assigned to a specific hardware unit. In digital signal processing (DSP) many algo rithms have a repetitive nature: the same computation has to be executed for ....

M.C. McFarland, A.C. Parker, and R. Cam- posano. High-level synthesis of digital systems. Proceedings of the IEEE, 78(2):301-318, Febru- ary 1990.

....specifications to enhance design reusability, and the ability to more effectively explore the different design tradeoffs between the area and performance of the resulting hardware. Previous work in high level synthesis addressed mainly general purpose processor and signal processing de signs [1]. In these designs, the behavior usually consists of a set of computations that are performed within a certain amount of time. Synthesis of these designs can produce cost effective implementations because the synthe sis system can take advantage of domain specific knowledge to optimize the ....

....to the synthesis of benchmark circuits and ASIC designs starting from behavioral level specification. We present the experimental results and conclude in Section 7. 2 Related Research The focus of most high level synthesis efforts todate has been on synthesizing and optimizing the data path [1]. While these systems have been effective in synthesizing certain types of designs and efficient algorithms have been developed to address many difficult synthesis problems, they do not adequately address the synthesis of ASIC designs with complex handshaking protocols and strict timing ....

M. McFarland, A. Parker, and R. Camposano, "The high-level synthesis of digital systems," Proceedings of the IEEE, vol. Vol. 78, no. No. 2, pp. pp. 301-318, Feb. 1990.

....designing fault tolerant system with optimal productivity, provides a synthesis method for the problem, and present extensive experimental results. Finally, we conclude our contribution in Section 6. 2 Previous Work Scheduling has been widely studied in many areas, such as behavioral synthesis [13], parallel processing [4] and hard real time systems [12] Recently, algorithm selection has been recognized as an important system level synthesis topic, and several approaches have been proposed [15] Behavioral synthesis provides the mechanism for design space exploration so that a variety of ....

.... hard real time systems [12] Recently, algorithm selection has been recognized as an important system level synthesis topic, and several approaches have been proposed [15] Behavioral synthesis provides the mechanism for design space exploration so that a variety of design goals can be optimized [13] [2] Much of the behavioral synthesis research have targeted the optimization of area, speed (throughput) and more recently power and testability. Relatively little work has been reported on behavioral level synthesis techniques for fault tolerant design. Raghavendra and Lursinsap [18] ....

M.C. McFarland, A.C. Parker, R. Camposano, "The High-Level Synthesis of Digital Systems," Proceedings of the IEEE, Vol. 78, No. 2, pp. 301-317, 1990.

....tasks assigned to the same processor was the most important factor in obtaining good designs. We have demonstrated the effectiveness of our algorithms on several multiple task examples. 1 Introduction Until now high level synthesis has concentrated on the synthesis of a single computational task [McF90]. In this paper we introduce the first high level synthesis algorithm for the creation of multi task application specific systems. By using information provided by hard real time scheduling methodologies and behavioral synthesis tools, we connect the synthesis process to operating systems ....

M.C. McFarland, A.C. Parker, R. Camposano: "The High-Level Synthesis of Digital Systems", Proceedings of the IEEE, Vol. 78, No. 2, pp. 301-317, 1990.

.... The complexity of modern digital circuits requires automated synthesis and optimization techniques that can explore a wide class of implementations choices using computer aided design (CAD) tools [1] High level synthesis is the process of generating RTL structure from a behavioral description [2]. The modules (functional units) allocated by high level synthesis algorithms are generated by module generators which are able to synthesize the layout of modules with high performance and device density. The modules are placed in module libraries and have identical physical information. Given ....

M.C. McFarland, A.C. Parker, and R. Camposano, "The high-level synthesis of digital systems," Proceedings of the IEEE, vol. 78, pp. 301--318, Feb 1990.

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M. C. McFarland, A. C. Parker, and R. Camposano, "The high-level synthesis of digital systems," Proc. IEEE, vol. 78, pp. 301--318, Feb. 1990.

No context found.

M. C. McFarland, A. C. Parker, and R. Camposano, "The high-level synthesis of digital systems," Proceedings of the IEEE, pp. 301--318, February 1990.

No context found.

M. McFarland, A. Parker, and R. Camposano, "The high-level synthesis of digital systems," Proc. IEEE, vol. 78, no. 2, pp. 301--318, Feb. 1990.

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Michael C. McFarland, Alice C. Parker, and Raul Camposano. The high-level synthesis of digital systems. Proceedings of the IEEE, 78(2):31 8, February 1990.

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M. C. McFarland, Alice C. Parker, and Raul Camposano, "The High-Level Synthesis of Digital Systems," Proceedings of the IEEE, vol. 78, no. 2, pp. 301--318, Feb 1990.

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M. C. McFarland, A. C. Parker, and R. Camposano, The high-level synthesis of digital systems, in Proceedings of the IEEE, vol. 78, pp. 301---318, 1990.

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M.C.McFarland, A.C.Parker, R.Camposano, "The high-level synthesis of digital systems", Proc. of the IEEE, special issue on "The future of computer-aided design", Vol.78, No.2, pp.301-318, Feb. 1990.

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M.C. McFarland, A.C. Parker, R. Camposano (1990). The high-level synthesis of digital systems. Proceedings of the IEEE 78, 301--318.

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