R. Walker and R. Camposano (eds.), A Survey of High-Level Synthesis Systems, Kluwer Academic Publishers, Boston, MA, 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....We report experimental results indicating the effectiveness of the proposed technique and summarize our ongoing work to further strengthen it. 1. Introduction High level synthesis (hls) systems generate register transfer level (rtl) designs from algorithmic behavioral specifications (Figure 1) [19, 15, 48, 8, 53, 26]. The rtl design consists of a data path and a controller. This paper is an extension to the work presented in the International Conference on Formal Methods in Computer Aided Design [29] Nov 1998. c fl 1999 Kluwer Academic Publishers. Printed in the Netherlands. The data path consists of ....

....if an operator is control dependent on a control operator then it is not scheduled until after the control operator is scheduled. Current scheduling algorithms in high level synthesis generally assume that control operators introduce sequential control flow points into the cdfg being scheduled [19, 15, 48, 8, 53, 26]. For example, 11 all operators inside a case statement are scheduled only after the deciding expression has been scheduled. All statements following the case statement are scheduled only after all the branches of the case statement are scheduled. All statements inside a while statement are ....

Walker, R. and R. Camposano: 1990, `A Survey of High-Level Synthesis Systems'. Kluwer Academic Publishers.

....high level synthesis tools. These same transformations can also serve as a basis for converting a VHDL process to a form suitable for generation of soft war. 1 Introduction VHDL is rapidly gaining acceptance as a behavioral specification language serving as input to high level synthesis tools [1, 2, 3, 4, 5, 6, 7] as well as to hardware software codesign tools [8, 9] ttowever, several of its constructs, while possessing great expressive power, are not easily handled by existing synthesis tools. Two such constructs are the wait statement and the signal, both having tithe based semantics. The wait ....

R. Walker and R. Camposano, A Survey of HighLevel Synthesis Systems. Kluwer Academic Publish- ers, 1991.

....In Proc. of EURO DAC 94, pp 226 231, Grenoble, France, Sept. 1994. 11] P. Ellervee, J. berg, A. Jantsch, A. Hemani, Neural Network Based Estimator to Explore the Design Space at System Level , In Proc. of the 4th Biennial Baltic Electronic Conference, pp 391 396, Tallinn, Estonia, Oct. 1994. [12] J. Isoaho, J. berg, A. Hemani, H. Tenhunen, HLS based DSP Optimization with ASIC RTL Libraries , poster paper) In VLSI Signal Processing VII, J. Rabaey, P.M. Chau and J. Eldon, editors, pp 218 225, IEEE Inc. New York, 1994. 13] A. Hemani, B. Svantesson, P. Ellervee, A. Postula, J. berg, ....

....This process is iterated until an acceptable solution is found. Such a methodology is termed specify explore refine methodology [15] Design space exploration is a complex task in general, but can be more manageable in a specific application domain 1.4. High Level Synthesis High Level Synthesis [10, 11, 12] is the task of translating a description of a design at the algorithmic level and translate it into a Register Transfer (RT) level description or an RT level netlist. Since most of the tool designers had been working with implementing DSP algorithms before the research started with HLS in the ....

R.A. Walker, R. Camposano, A Survey of High-Level Synthesis Systems, Kluwer Academic Publishers, Boston, 1991.

....description [4] of the protocol similar to the protocol functional specification that is mapped into a structural description through HLS techniques. Of special concern in the HLS step is the use of a sheduling algorithm well suited to the synthesis of control flow dominated behavioral compilers [5]. In this case, the Dynamic Loop Scheduling (DLS) 6, 7, 8, 9] algorithm is employed. The resulting structural description is then used as input of the logical synthesis tool Synopsys [10] and finally the Opus [11] tool generates the circuit layout. In this work two protocols, the IPv6 and the ....

Walker, R., Camposano, R., A Survey of HighLevel Synthesis Systems. University of California, Irvine: Kluver Academic Publishers, 1991.

....The authors are with C C Research Laboratories, NEC USA, Princeton, NJ 08540 USA. IEEE Log Nmnber 9410364. improvements between factor of two and several orders of magnitude. On the other hand, only minor improvements in these goals have been reported when only scheduling and assignment are used [39]. Clearly, it is important to evaluate the potential of transformations for testability improvements during the high level design process. In this paper, we present a technique which uses a variety of transformations to reduce the area overhead required by Design For Testability (DFT) techniques ....

....V) during the application of transformations. II. PREVIOUS RELATED WORK Related work is outlined along two lines of research: highlevel synthesis techniques for testability and transformations. The mandatory tasks during high level synthesis are allocation, scheduling, and assignment [27] [39], all of which have been shown to have significant impact on the testability of the synthesized designs. Existing high level synthesis for testability techniques can be broadly classified according to the testing methodology targeted: BIST, gate level sequential ATPG, or hierarchical test pattern ....

[Article contains additional citation context not shown here]

R. Walker and R. Camposano, Survey of High-Level Synthesis Systems. Boston, MA: Kluwer, 1991.

....Resource Concurrency NFA Composition Cartesian Product and Pruning NFA Exploration Shortest Paths Performance Metrics Execution Sequences for Synthesis New NFA Models 6 1.4 Related Work 1.4. 1 High Level Synthesis ABSS is most related to work in high level synthesis [35] 39] 40] 66] 88][137]. High level synthesis is an automated process that transforms an algorithmic specification of a digital system s behavior into a hardware structure that implements the behavior. High level synthesis offers simple and fast design specification, short and highly automated design cycles, and ....

R. A. Walker and R. Camposano, A Survey of High-Level Synthesis Systems, Kluwer Academic Publishers, 1991.

....the literature. These efforts include Flamel [13] a Pascal to hardware compiler, IBM s HIS system [14] which translates a VHDL behavioral description into a synchronous digital machine, and Cyber [15] which compiles programs in C and BDL into ASIC chips. In addition, Camposano [16] and Walker [17] report a survey of different highlevel synthesis systems. Most of the above approaches differ with regard to the high level hardware description language, optimization and transformation techniques, and scheduling and allocation algorithms. However, they share a common underlying model of ....

Robert A. Walker and Raul Camposano, editors. A Survey of High-Level Synthesis Systems. Kluwer Academic Publishers, 1991.

....force directed scheduler as an indicator of the number of units that might be needed, and thus to guide the selection of control steps and operations for scheduling. This approach has since then been refined in terms of speed, efficiency, and the number of covered issues in more than 20 schedulers [Wal91]. These ideas are the starting point for the development and quantification of uniformity measures. The graph computation and relevant measures on these graphs which quantify the property class are presented in the next section. 4.1.1.1 Calculating Uniformity Graphs As the exact times in which ....

R. Walker, R. Camposano (ed.), A Survey of High-Level Synthesis Systems, Kluwer Academic, Boston, 1991.

....However, there is a strong experimental evidence that they are most effective at the highest levels of abstractions, such as system and in particular behavioral synthesis. Transformations only received widespread attention in high level synthesis [Ku and Micheli 1992; Potkonjak and Rabaey 1992; Walker and Camposano 1991]. Comprehensive reviews of use of transformations in parallelizing compilers, stateof the art general purpose computing environments, and VLSI DSP design are given in [Banerjee et al. 1993] Bacon et al. 1994] and [Parhi 1995] respectively. The approaches for transformation ordering can be ....

Walker, R. and Camposano, R. 1991. A Survey of High-level Synthesis Systems. Kluwer, Norwell, MA.

.... and subroutines [McFarland et al. 1990] more recently a number of high level synthesis systems targeted synthesis of hierarchical computations (with loops and subroutines) and stressed the importance of the associated global optimization techniques across the lowest levels of the hierarchy [Walker and Camposano 1991. The trend in high level synthesis research is to consider higher levels of abstraction and larger chunks of a system design; this trend continues unabated thanks to both application and implementation factors. The size of average embedded and DSP applications has been approximately doubling ....

R.A. Walker, R. Camposano: "A Survey of high-level synthesis systems", Kluwer Academic, Norwell, MA, 1991.

....behavioral or architectural synthesis) are maturing and may provide an issue to the design bottleneck. These tools allow to produce complex designs starting from a behavioral description. Protocol design require specific HLS tools, generally called control flow dominated behavioral compilers[24]. These tools are able to handle large control structure including sophisticated handshaking and non structured sequences. However most of these compilers present an inescapable 2 drawback, the compilation results depends on the quality of the input description. This comes from the fact that the ....

Walter R.A., Camposano R. , A Survey of High-Level Synthesis Systems, Kluwer Academic Publishers, 1991.

....these techniques is that they are very time inefficient and hence, the motivation for the efforts to estimate power at a higher level of abstraction. 1. 2 Behavioral Synthesis Behavioral Synthesis is the process of generating a register level design from an algorithmic behavioral specification [3, 2]. A typical behavioral synthesis system is as shown in (Figure 1.1) The inputs to the system are the behavioral specification, a module library and the user constraints. The behavioral specification can be written in a high level general purpose language such as C or in a Hardware Description ....

R. A. Walker and R. Camposano (eds.), "A Survey of High-Level Synthesis System", Kluwer Academic Publishers, 1991.

....Although many synthesis systems use transformations [1, 17] on their internal representation, these transformations do not try to reduce the impact of syntactic differences in the input descriptions on the synthesized design. They are mainly intended for the purpose of optimizing the final design [16]. For example, none of the descriptions from Figure 1(a) b) or Figure 2(a) b) would be influenced by published transformation techniques. A simple solution to avoid the inefficiences caused by syntactic differences is to force the designer to write descriptions that fits the algorithm used ....

R.A. Walker and R. Camposano, A Survey of High-Level Synthesis Systems, Kluwer Academic Publishers, 1991.

....phase. Future research will concentrate on automating this design decision. Comparison with other approaches The synthesis process used within the MOVE framework has much in common with high level synthesis (HLS) systems which have been developed [Bre91, Cam90, CW91, GDWL92, KGD90, MLD92, WC91] they both aim at the automatic mapping of a functional specification into a structural description. There are several differences, though: ffl Most HLS systems do not accept full blown applications written in commonly used imperative languages. Usually their usage is restricted to input from ....

Robert A. Walker and Raul Camposano, editors. A survey of high-level synthesis systems. Kluwer academic publishers, 1991.

....in the eld. 1. Introduction Over the last twenty years, advances in circuit fabrication technology have increased device densities and as a consequence, they have increased design complexity. To manage continuously emerging tasks, designers have moved towards higher levels of abstraction [31] and language based design descriptions [14, 16, 27, 28, 21] which are closer to the way they conceive their work. However, each design must be described, eventually, at the lowest level (e.g. layout masks) in order to be fabricated. The transformation from one level of abstraction to the next ....

....to the way they conceive their work. However, each design must be described, eventually, at the lowest level (e.g. layout masks) in order to be fabricated. The transformation from one level of abstraction to the next is performed by various synthesis processes. High level or behavioral synthesis [11, 18, 19, 30, 31], is dened as the transformation of behavioral circuit descriptions into register transfer level (RTL) structural descriptions that implement the given behavior while satisfying user dened constraints. Today, with the adoption of standard Hardware Description Languages (HDLs) like VHDL [2, 3] or ....

R. A. Walker and R. Camposano. A Survey of High-Level Synthesis Systems. Kluwer Academic Publishers, 1991. 58

....with signal assignments and wait statements in behavioral specifications. 1 Introduction A high level synthesis system generates register level designs to implement the given behavioral specification subject to constraints on area, throughput rate, clock speed and other performance attributes [1, 2, 3, 4, 5]. These designs are synchronous and incorporate two interacting components: a data path and a controller. The primary focus in the area of control synthesis so far, has been in developing efficient techniques for state assignment and output encoding for finite state machines [6] There has been ....

R. Walker and R. Camposano. "A Survey of High-Level Synthesis Systems". Kluwer Academic Publishers, 1991. Ellip TLC Move m/c Fifo Viper Shuffle Lines in Behavior Spec. 83 76 148 118 408 472

....and low power methodologies. In this paper, we present a behavioral synthesis system known as the Profile Driven Synthesis System (PDSS) which synthesizes low power designs. Behavioral Synthesis is the process of generating a register level design from an algorithmic behavioral specification [1, 2]. Inputs to the system are the behavioral specification, a module library and user constraints such as area, clock speed etc. The behavioral specification can be written in a high level general purpose language like C or a Hardware Description Language like VHDL. The module library consists of ....

R. A. Walker and R. Camposano (eds.), A Survey of High-Level Synthesis System, Kluwer Academic Publishers, 1991.

....so useful. Theorem Proving Guided Development of Formal Assertions in a Resource Constrained Scheduler for High Level Synthesis 1 Motivation Much research has been performed in High Level Synthesis (HLS) and relatively mature implementations of various HLS algorithms have started to emerge [21]. High level synthesis tools are large and complex software systems which are prone to conceptual and programming errors like any other software system. Errors in the system could have disastrous and often expensive ramifications since as they could lead to the synthesis and finally fabrication ....

R. Walker and R. Camposano. "A Survey of High-Level Synthesis Systems". Kluwer Academic Publishers, 1991. 21

....the sum of execution times of the individual task is longer than the total available time, the only implementation option is multiprocessor platform. Both traditional behavioral synthesis and emerging system synthesis, however, have been focused on synthesis of single task applications [11] 27] [49]. Recently, Potkonjak and Wolf developed an algorithm for the synthesis of multitask applications at the behavioral level [34] A few research groups addressed synthesis of hard real time systems [35] 52] but usually under restricted design scenarios. This research project has been motivated ....

....Gajski s statement that scheduling is the single most important behavioral synthesis step [27] has been widely quoted. Recently, however, it was realized that the scheduling in the traditional behavioral synthesis usually does not have high impact on the quality of the final implementation [49] and that other synthesis optimization tasks, such as transformations, usually make greater differences in the final results [5] 16] 22] 32] 33] Moreover, it was reported that the available scheduling algorithms often produce optimal results [6] 36] 39] The focus of behavioral synthesis ....

[Article contains additional citation context not shown here]

R. A. Walker and R. Camposano. A Survey of High-level Synthesis Systems. Kluwer Academic, Norwell, MA, 1991.

No context found.

R. Walker and R. Camposano (eds.), A Survey of High-Level Synthesis Systems, Kluwer Academic Publishers, Boston, MA, 1991.

No context found.

R.A. Walker, R. Camposano, "A Survey of High-Level Synthesis Systems", Kluwer Academic Publishers, Boston, Ma, 1991.

No context found.

R. A. Walker and G. Boriello. A Survey of High-Level Synthesis Systems. Kluwer Academic Publishers, Borton/London/Dordrecht, 1991. 10

No context found.

R.A. Walker and R. Camposano, A Survey of High-Level Synthesis Systems, Kluwer Academic Publishers, 1991.

No context found.

R. A. Walker and R. Camposano (eds.), "A Survey of HighLevel Synthesis System", Kluwer Academic Publishers, 1991.

No context found.

R.A. Walker, R. Camposano (ed.), "A survey of high-level synthesis systems", Kluwer Acad. Publ., 1991.

First 50 documents

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC